Memory scheduling method and device

Abstract

The embodiment of the invention discloses a memory scheduling method. The memory scheduling method is used for simplifying memory division and improving the scheduling efficiency. The method provided by the embodiment of the invention comprises the following steps: dividing a memory into a plurality of memory blocks according to a pre-set rule, wherein the size of each memory block is a fixed value; when receiving a target task request, determining a plurality of sub-requirements corresponding to the target task request, wherein the size of each sub-requirement is smaller than the size of the memory block with the maximum capacity in the plurality of memory blocks; establishing a mapping relation of the plurality of sub-requirements and the plurality of memory blocks; and according to the mapping relation of the plurality of sub-requirements and the plurality of memory blocks, applying for a corresponding memory block set corresponding to the target task request from a memory management module. The embodiment of the invention also provides a scheduling device which is used for simplifying the memory division and improving the scheduling efficiency.

Description

technical field [0001] The invention relates to the communication field, in particular to a memory scheduling method and device. Background technique [0002] With the continuous improvement of users' requirements on processor performance, the problem of power consumption limits the development of single-core processors to continuously improve performance, and more and more multi-core processors have emerged as the times require. In a multi-core processor, multiple processors operate in parallel, and the tasks to be processed are decomposed into several parts. According to a certain scheduling principle, each part is scheduled to be executed on a core by the functional module responsible for scheduling. In a multi-core processor, the capacity, speed and price of the memory often contradict each other. The faster the memory, the higher the price; the larger the capacity, the slower the speed. Therefore, a multi-core processor usually adopts a storage system composed of multi...

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Problems solved by technology

[0004] Whether the above method is memory division or memory application, more complex calculations are required, and the implementation complexity of the solution is high.

In addition, when the scheduling core applies for and releases memory, it may do merge processing, and the efficiency is uncontrollable. When there are many tasks, the amount of calculation will be large, and the efficiency will be very low.

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