A PIE coding demodulation method with ultra-low power consumption

Abstract

The invention aims to overcome the defects in the prior art, provides a PIE coding demodulation method with ultra-low power consumption and a circuit architecture, greatly reduces the overall power consumption of a circuit on the premise that the performance is not reduced, adjusts the sampling reference, and ensures the sampling accuracy. In order to achieve the purpose, the PIE coding demodulation method with ultra-low power consumption is realized based on a demodulation coding circuit, the demodulation coding circuit comprises a counter formed by connecting N stages of registers in series,and a system clock only drives a first stage of register; Each level of register is driven by the output negation of the previous level of register; Therefore, the driving clock of the Nth-level register becomes SYS _ CLK/2 ^ (N-1). By the adoption of the technical scheme, when the number of bits of the counter is larger than two, the total power consumption of the counter is remarkably lower than that of a counter of a common structure. Therefore, the overall energy consumption of the circuit is reduced after the power is reduced, and the later optimization of the overall structure is facilitated.

Description

technical field [0001] The invention relates to the technical field of radio frequency identification, in particular to a decoder suitable for PIE encoding. Background technique [0002] The full name of PIE (Pulse interval encoding) encoding is pulse width encoding. The principle is to represent data by defining different time widths between pulse falling edges. According to the standard, the data frame sent by the reader to the tag consists of SOF (start of frame signal), EOF (end of frame signal), data 0 and 1. [0003] The PIE encoding and demodulation method in the prior art usually samples and counts the delimiter, Tari, RTcal, TRcal and Data respectively. However, there is still a problem of excessive power consumption, which requires further optimization. The delimiter was originally designed to calibrate the deviation of the system's own clock. With the development of technology, the consistency of the clock is optimized from all aspects of design, production and ...

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