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A Method of Parallel Realization of Frame Synchronization in High Speed ​​Data Transmission System Based on FPGA

A system frame, high-speed technology, applied in the field of FPGA-based high-speed data transmission system frame synchronization parallel implementation

Active Publication Date: 2021-01-29
湖南国科锐承电子科技有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, in the high-speed data transmission system involved in this method, the system sampling rate is as high as several GHz, and the existing hardware and software cannot be realized through a single channel. Therefore, multi-channel parallel design is required

Method used

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  • A Method of Parallel Realization of Frame Synchronization in High Speed ​​Data Transmission System Based on FPGA
  • A Method of Parallel Realization of Frame Synchronization in High Speed ​​Data Transmission System Based on FPGA
  • A Method of Parallel Realization of Frame Synchronization in High Speed ​​Data Transmission System Based on FPGA

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Embodiment 1

[0050] The highest data transmission rate of the system is 6 Gbit / s, and the sampling rate of AD is 2.6 GHz, which is output in parallel by 8 routes, and the clock of each route is 325 MHz. The frame format of the high-speed data transmission system is attached figure 1 As shown, it includes frame header and data. The data part adopts OFDM modulation of QPSK or 64QAM. There are 15 OFDM symbols in one frame, each symbol contains 1024 subcarriers, and the CP length is 1 / 32 symbol length.

[0051] After quadrature down-conversion and filtering processing, each subcarrier is sampled according to one sample point, and the frame header has a total of 1056 sample points. BPSK single-carrier modulation is adopted, and the length is the same as that of one OFDM symbol. The length of the register for receiving signals is designed to be 1063, and the length of the register for the square sum of the signal amplitudes of 8 channels is 132.

[0052] The implementation process of receivin...

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Abstract

The invention discloses a method for parallel realization of frame synchronization of a FPGA-based high-speed data transmission system. Compared with the existing method, the method has certain advantages. First, a step factor is introduced into the M&M algorithm d , in order to reduce the computational complexity of the algorithm, the estimation range is variable, and the loss of estimation accuracy is small. Secondly, under a certain estimation accuracy, its estimation range is larger than that of the Fitz algorithm, because it separates the estimation range and estimation accuracy, avoiding the following The shortcoming of achieving high estimation accuracy at the expense of sacrificing the estimation range; through experimental comparison, this method is more flexible and applicable than the M&M algorithm and the Fitz algorithm.

Description

technical field [0001] The invention relates to the technical field of wireless communication synchronization, in particular to a method for parallel realization of frame synchronization in an FPGA-based high-speed data transmission system. Background technique [0002] Orthogonal frequency division multiplexing (OFDM) technology is a special multi-carrier modulation technology. Due to its advantages of effectively resisting the effects of multipath fading, high spectrum utilization, easy implementation, and easy use in combination with other access methods, It has been widely used and is the key technology of the next generation of mobile communication. Different from single-carrier systems, OFDM systems have high requirements on synchronization technology, because the inter-symbol interference and inter-subcarrier interference introduced by synchronization errors will destroy the orthogonality between sub-carriers and affect system performance. Therefore, as described in ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L27/26
CPCH04L27/2656
Inventor 胡登鹏姜南朱江杨虎高凯杨军李二保王新建
Owner 湖南国科锐承电子科技有限公司