8results about How to "Reduce calculation delay" patented technology

The invention, which relates to the field of FPGA and machine learning, discloses a high-flow-degree MambaV2 hardware acceleration system with an optimized calculation sequence based on FPGA, comprising a preceding stage module, a tensor expansion module, a hidden layer state calculation module, an output state calculation module, a residual multiplication normalization module and an output linear layer module. The calculation process of the MambaV2 algorithm is divided into a plurality of pipeline levels, and a data stream is output in a pipeline form. According to the method, an original algorithm structure is not changed, the operation sequence of a hidden layer state equation in an original algorithm is changed, an algorithm for optimizing the calculation sequence is provided, the number of times of operation is reduced, cache consumption is reduced, the MambaV2 model is deployed and reasoned on an FPGA, the edge scene deployment requirement is met, customized acceleration of the FPGA is utilized, and data streams are adjusted, so that the edge scene deployment efficiency is improved. The pipeline design of the whole algorithm is realized, the utilization rate of computing resources is improved, the problem of data blocking is solved, and computing delay and cache consumption are reduced.

The invention discloses a four-point piezoelectric driving fast oscillating mirror control system based on STM32. The four-point piezoelectric driving fast oscillating mirror control system comprises a piezoelectric driving fast oscillating mirror, a PSD position sensitive detector, an AD acquisition module, a DA output module, a piezoelectric driving controller, a piezoelectric actuator, an STM32 control module and a PSD position sensitive detector. An electric signal of an object to be tracked is transmitted back to the STM32 controller through the AD acquisition module, the driving voltage of each piezoelectric ceramic actuator is obtained through an improved ADRC algorithm, then the STM32 controller sends a control signal through the DA output module, and the control of the rotation angle of the fast oscillating mirror is completed through the driving of the piezoelectric ceramic actuators. According to the method, the parallel computing advantage of the STM32 is fully utilized, the system delay is reduced, high-precision, real-time and synchronous multi-piezoelectric compensation and control are realized, and the method is of great significance to researches such as closed-loop testing of a fast oscillating mirror controller, piezoelectric ceramic hysteresis nonlinear modeling and model parameter identification.

The invention belongs to the technical field of digital signal processing, and particularly discloses a space-time interference cancellation algorithm parallelization FPGA implementation device and method, and the device comprises an input vector generation module which delays and arranges reference signals of multiple channels, and obtains space-time input vectors of the reference signals; the correlation matrix calculation module is used for acquiring an autocorrelation matrix and a cross-correlation vector; the matrix decomposition module is used for performing matrix decomposition on the autocorrelation matrix to obtain an upper triangular matrix; the weight determination module is used for carrying out weight solving by utilizing the upper triangular matrix and the cross-correlation vector to obtain an optimal weight; the delay matching module is used for delaying the reference signal and carrying out time sequence alignment on the reference signal and the optimal weight to obtain a delay matching result; and the weighting and combining module is used for weighting the reference signals subjected to the time sequence alignment according to the optimal weight to obtain weighted signals and combining the weighted signals with the received signals so as to realize interference elimination of the received signals. According to the invention, the real-time tracking capability can be improved and the processing delay can be reduced.

This invention relates to the field of robot control technology, specifically to an end-to-end closed-loop control method and system for robots based on multimodal perception fusion. It includes: a perception access layer for standardized access to data from multiple sensor types; a fusion processing layer for spatiotemporal alignment and multimodal fusion processing of the standardized access data; a decision control layer for generating execution instructions based on the fusion processing results; and an execution feedback layer for feeding back the execution status to the fusion processing layer to form closed-loop control. This technical solution can solve the problems of standardized access and real-time fusion of multi-source heterogeneous data, and construct a closed-loop control architecture with high fault tolerance and low latency.

This invention relates to the field of image processing technology, and in particular to a hardware implementation algorithm for image connected component labeling. The hardware implementation architecture of the connected component labeling algorithm adopts a pixel-based approach for connected component labeling. The equivalence table structure uses a one-dimensional array. The computational architecture includes an initial labeling and equivalence table storage module, an equivalence table copying and updating module, a coordinate recording and updating module, and an adjacent row label storage and comparison module. Based on the characteristics of connected components in binary images, this invention performs copying and updating operations on the equivalence table according to the image behavior cycle, effectively reducing processing latency and forming a high-efficiency computational architecture for connected component labeling based on FPGA.

The present disclosure provides a global pooling method and a multi-core system for a neural network, the method comprising: receiving point data of the data to be processed inputted sequentially by the previous network layer; after each point data is received, performing a preset pooling operation based on the currently received point data until all the point data of the data to be processed are pooled. Based on the solution provided by the present disclosure, point operations can be used instead of graph operations in the pipeline operation of the multi-core system, that is, after each point data is received, it will be processed once to obtain an intermediate pooling result, until the final pooling result of the data to be processed is finally obtained, thereby reducing the calculation delay.

The invention discloses a partial discharge signal extraction method and device for a transformer active protection device, and the method comprises the steps: collecting a partial electric signal of a transformer, and marking a preliminary suspicious moment if the partial electric signal is greater than an electric signal threshold value; reading back local electric signals at a plurality of sampling moments before the preliminary suspicious moment, acquiring local electric signals at a plurality of sampling moments after the preliminary suspicious moment, and performing Fourier transform on the local electric signals one by one to obtain frequency spectrum signals; selecting signal amplitudes of characteristic frequency points in the frequency spectrum signal, and comparing the signal amplitudes with an amplitude threshold one by one; and if a plurality of signal amplitudes are simultaneously greater than the amplitude threshold, marking the preliminary suspicious moment as a height suspicious moment, and reporting the height suspicious moment to the active protection device. By adopting the technical scheme, the requirements on the operand and the storage capacity are effectively reduced, and the real-time operation on the transformer can be realized.

The invention discloses a networking protocol design method cooperating with air computing in a high confrontation environment. The networking protocol design method mainly solves the problems that in the prior art, self-organizing network data transmission is poor in reliability, high in protocol complexity and large in control overhead. According to the implementation scheme, a networking protocol frame structure comprising a control time slot and a service time slot is designed, and the whole network topology is obtained in the control time slot; calculating the shortest path according to the whole network topology; calculating Y secondary short paths to be searched according to the shortest path, and selecting m paths with the same hop count from the Y paths as use paths; the source node searches for time slots outside a two-hop range for all nodes; according to the found time slots outside the two-hop range, the source node finds all available time slots for the relay node on the path according to the adjacent matrix of the node; and filling all available time slots of all relay nodes on the path into a data packet, and distributing the available time slots to the relay nodes. The method is high in reliability, low in protocol complexity and low in control overhead, and can be used for the MAC layer and the network layer of the self-organizing network of the unmanned system.