42results about How to "Reduce calculation delay" patented technology

The invention discloses an image guiding and tracking method based on prediction, which comprises the following steps: 1, inputting image sequences and a breathing status feature set of a tumor anatomical structure; 2, establishing a status association database; 3, acquiring real-time images and breathing status features; 4, predicting the delayed breathing status features, and determining the image sequences in a corresponding tumor shape varying section; 5, registering the real-time images with the image sequences in the tumor shape varying section one by one in an interested area; 6, selecting an optimal tumor shape image from registration results; and 7, outputting the image of the tumor anatomical structure. The image guiding and tracking method based on the prediction establishes the correlation between breath and tumor movement by the quantification and analysis on the breathing statuses, predicts the breath and tracks the movement according to the correlation, and improves the efficiency and the accuracy of tracking a dynamic tumor in real time.

The invention discloses a microgrid multi-inverter parallel-control method based on frequency division virtual complex impedance, which is suitable for a multi-inverter parallel-control system with a nonlinear load for a low-voltage microgrid. The microgrid multi-inverter parallel-control method comprises the following steps: performing frequency division on a line current by virtue of a band pass filter by adopting a robust droop control strategy of resistance equivalent output impedance, simultaneously multiplying a fundamental current by a virtual complex impedance containing a resistance-capacitance component, designing that each parallel connection inverter output impedance is resistive in a fundamental band; and respectively multiplying each high-frequency current by different virtual inductive impedances, indicating that a harmonic frequency band inverter output impedance is inductive so as to be limited by the robust droop control strategy of resistance equivalent output impedance, so that the influence of a high-frequency harmonic current to inverter parallel-control is avoided. According to the microgrid multi-inverter parallel-control method, the defect of a conventional method is overcome, and good control effect is achieved in the multi-inverter parallel-control system with the nonlinear load for the low-voltage microgrid.

A method for calculating the least value of the circulating grading to the LDPC decoding and a realizing device thereof belong to the field of the digital information transmission technique. The method uses a fundamental least value calculating module which is composed of a comparator and a selector, and realizes the least value calculation of the horizontal calculating unit in the low-density check code encoder basing on the least summation algorithm and the improved algorithm. The designing process of the low-density check code encoder can be simplified, and the consumption quantity of the logical resource of the horizontal arithmetic unit in the encoder can be reduced. The least value calculating method basing on the invention and the realizing device thereof has the advantages of directly designing out the horizontal arithmetic unit of the production line, decomposition to the time delay path of the horizontal arithmetic unit, increase to the clock frequency of the encoder and increase to the capability of the turnover rate of decoding.

The invention provides an alternating-current fault detection method for high-voltage direct-current power transmission. The alternating-current fault detection method for high-voltage direct-current power transmission comprises the following steps of obtaining the three-phase voltage of a current conversion bus and three-phase currents of outgoing lines of the current conversion bus; obtaining a voltage zero-sequence component value and a rotating vector amplitude of the current conversion bus according to the three-phase voltage of the current conversion bus, and obtaining current zero-sequence component values and rotating vector amplitudes of the outgoing lines of the current conversion bus according to the three-phase currents of outgoing lines of the current conversion bus; obtaining power zero-sequence component values and power rotating vector amplitudes of the outgoing lines of the current conversion bus; comparing the values and the amplitudes with the set values and the set amplitudes respectively to obtain the fault detection result. The alternating-current fault detection method for high-voltage direct-current power transmission is high in speed and accuracy, and meets the requirement of high-voltage direct-current power transmission for fault detection, and valuable information is provided for the defense commutation failure of a control system for high-voltage direct-current power transmission.

The invention provides a task processing method, edge computing equipment, computer equipment, and a computer-readable medium. The method comprises the following steps: receiving tasks sent by network equipment; determining distribution types of the tasks, dividing the tasks into task units according to the distribution types, and putting the task units into a task pool; according to the types of the task units in the task pool, determining the issuing priority of the task units in the task pool, wherein the types of the task units are the distribution types of the tasks to which the task units belongs; determining to-be-processed task units according to the issuing priority; if the current processing capability of edge computing equipment does not meet a preset first requirement, determining first network element equipment, and sending the to-be-processed task units to the first network element equipment. According to the invention, when computing power resources of the edge computing equipment are insufficient, the first network element equipment is selected from a peripheral network element group to carry out task transfer computing, so that the computing power of the edge computing equipment is improved, and the task computing delay can be reduced at the same time.

The invention discloses an FPGA-based three-point piezoelectric driving fast steering mirror hysteresis compensation control system, which comprises an FPGA hysteresis compensation control module, an SGS micro-displacement sensor, an SGS micro-displacement signal conditioning and acquisition circuit, a piezoelectric ceramic driving circuit, an upper computer and a three-point piezoelectric driving fast steering mirror, and is characterized in that the three-point piezoelectric driving large-aperture fast steering mirror is a controlled object, the SGS micro-displacement sensor is integrated in a piezoelectric ceramic actuator, the SGS micro-displacement signal conditioning and acquisition circuit is connected with the FPGA hysteresis compensation control module, the piezoelectric ceramic driving circuit is connected with the FPGA hysteresis compensation control module, and the upper computer is communicated with the FPGA through a 422 interface. According to the system, the parallel processing characteristic of the FPGA is fully utilized, deployment of a PI inverse model based on parallel connection of multiple Stop operators on the FPGA and parallel hysteresis compensation control of multiple piezoelectric ceramic actuators are completed, the calculation delay of the system is shortened, the response speed of the system is increased, and high-precision, real-time and synchronous multi-piezoelectric compensation and control are achieved.

The invention provides a method, a device and a system for modulating a zero sequence voltage pulse width of a three-phase four-legged APF (active power filter). The method comprises the following steps of solving a zero sequence component according to a reference value of a voltage of midpoints of legs A, B and C of the three-phase four-legged arm APF to a midpoint of a leg N of the three-phase four-legged arm APF; controlling a pulse duty ratio according to a reference value of a voltage of a calculating point N of the three-phase four-legged APF to a point O of a cathode of a direct-current bus capacitor and a switch tube of the leg N; and solving a voltage of the midpoints of the legs A, B and C of the three-phase four-legged APF to the point O of the cathode of the direct-current bus capacitor and a corresponding duty ratio. A zero sequence voltage linear control pulse width modulation strategy is applied to the three-phase four-legged APF. Compared with the traditional 3D-SVPWM (three-dimensional space vector pulse width modulation) strategy, the zero sequence voltage linear control pulse width modulation strategy is easy to implement and can reduce calculation delay and requirements on main frequency; and the response speed of the three-phase four-legged APF can be increased further, the harmonic compensation accuracy of the three-phase four-legged APF can be improved, hardware investment is saved, and the method has an important practical significance on practical degree of a project of the three-phase four-legged APF.

The invention discloses an FFT calculation method for high-precision navigation. The FFT calculation method comprises the following steps: introducing an FFT8 butterfly-shaped accumulation calculationunit, four groups of butterfly-shaped accumulation and addition calculation units, a control unit and a data selection unit; obtaining the calculation type of the FFT calculation, employing an FFT8 butterfly-shaped accumulation calculation unit and four groups of butterfly-shaped accumulation-multiplication-addition calculation units to carry out calculation for a plurality of times, and completing the FFT calculation. The invention also discloses a calculation module for realizing the FFT calculation method for high-precision navigation, and a chip comprising the FFT calculation method for high-precision navigation and the calculation module. According to the method, logic resources are simplified into 30 adders, 4 multipliers and some simple control logics, and the maximum utilization rate of the adders and the multipliers is realized by adopting accurate pipeline control. Meanwhile, the calculation delay is relatively low, the resource utilization rate is higher, and the area of the chip module is effectively reduced.

The invention provides a train braking method and device, a storage medium and electronic equipment, and relates to the technical field of train network control. The method comprises the steps that when a braking instruction is received, calculating an electric braking force needed by a train; acquiring a current available DCU in the train; distributing the electric braking force needed by the train to the current available DCU according to a preset algorithm, and obtaining the electric braking force needing to be executed by each DCU; and sending the electric braking force needing to be executed by each DCU to the corresponding DCU, so that each DCU executes electric braking according to the corresponding electric braking force needing to be executed until the train speed is zero. According to the method provided by the invention, the accuracy of braking and parking of the train can be improved, so that the occurrence frequency of mark lacking or mark rushing of the train is reduced.

The invention discloses a method for automatically extracting an initial frame image target in target tracking, which comprises the following steps of: sequentially carrying out manual coordinate selection, image enhancement, significance detection and morphological processing on an input image, and then calculating a corrected coordinate; compared with other methods based on deep learning, the rapid automatic extraction method is small in calculation amount, low in calculation delay, adaptive and controllable in process, and very suitable for deployment and application of an embedded platform with computing power limitation.

The invention relates to an agricultural Internet of Things task overall planning method and system, and the method comprises the steps that a maximum utility function of each task node is determined according to a mathematical module through the game relation between M service nodes and N task nodes; at the t' moment, the service nodes send a computing power efficiency strategy to the N task nodes according to the computing power demand of each task node; each task node obtains a computing power demand strategy of each task node through first iteration of set times according to the received computing power efficiency strategy and the corresponding maximized utility function; whether a second iteration stop condition is met or not is judged; if the second iteration stop condition is not met, updating is carried out according to the set step length, and the step that the service nodes send the computing power efficiency strategy to the N task nodes according to the computing power demand of each task node at the t moment is returned; and if the second iteration stop condition is met, a computing power efficiency strategy sent by each service node and a computing power demand strategy of each task node is determined. According to the invention, the calculation time delay is reduced.

The invention provides a global pooling method of a neural network and a many-core system. The method comprises the steps of receiving point data of to-be-processed data input by a previous network layer in sequence; and after each piece of point data is received, executing a preset pooling operation based on the currently received point data until pooling of all point data of the to-be-processeddata is completed. Based on the scheme provided by the invention, the point operation can be used for replacing the graph operation under the line pipeline operation of the many-core system, that is,after each point data is received, the point data is processed once to obtain the intermediate pooling result until the final pooling result of the to-be-processed data is finally obtained, so that the calculation delay is reduced.

The invention provides an underwater sensor and a positioning system. The underwater sensor comprises a ReRAM and a controller, and the controller is connected with the ReRAM; wherein the ReRAM comprises a memory module and an Euclidean measurement module; the memory module is used for caching input data; the Euclidean measurement module comprises a plurality of parallel measurement modules, and each parallel measurement module comprises an addition calculation module, an extraction calculation module and a plurality of parallel calculation modules; the parallel computing module comprises a first subtraction array and a first multiplication array; the parallel computing module is used for performing parallel computing on each addend in the Euclidean metric formula; and the addition calculation module is used for completing a summation process of operation results of all units of the parallel calculation module and taking the results as input data of the evolution calculation module.