FFT (fast Fourier transform) butterfly operation hardware implementation circuit supporting complex multiplication

A butterfly operation and complex multiplication technology, applied in the field of FFT butterfly operation hardware implementation circuit, can solve the problems of high power consumption, short development time, difficult to meet DSP chips, etc., to reduce hardware overhead, reduce standardized operations, The effect of reducing the calculation delay

Active Publication Date: 2016-11-30
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

The DSP programming implementation method has a short development time, but consumes a lot of power
In some special occasions, the required signal processing speed is extremely high, and higher requirements are placed on the performance, power consumption and efficiency of the FFT algorithm. It is difficult to meet the above requirements by using a general-purpose digital signal processor DSP chip

Method used

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  • FFT (fast Fourier transform) butterfly operation hardware implementation circuit supporting complex multiplication
  • FFT (fast Fourier transform) butterfly operation hardware implementation circuit supporting complex multiplication
  • FFT (fast Fourier transform) butterfly operation hardware implementation circuit supporting complex multiplication

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Embodiment Construction

[0024] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0025] For large-scale FFT calculations, the Cooly-Tukey FFT algorithm is usually used. The Cooly-Tukey FFT algorithm adopts the idea of ​​​​divide and conquer, and uses two-dimensional FFT simulation to realize a large-scale one-dimensional FFT (N). For N=N 1 *N 2 FFT of points can be done with N 2 N 1 Point and N 1 N 2 Point FFT algorithm to achieve, the iterative formula is as follows:

[0026] X [ k 1 N 2 + k 2 ] = Σ n 1 = 0 N 1 - 1 [ e ...

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Abstract

The invention discloses an FFT (fast Fourier transform) butterfly operation hardware implementation circuit supporting complex multiplication. The circuit comprises a real part calculation module and an imaginary part calculation module, wherein the real part calculation module is used for calculating a real part in complex multiplication and calculating real parts of X and Y in butterfly operation, and the imaginary part calculation module is used for calculating an imaginary part in complex multiplication and calculating imaginary parts of X and Y in butterfly operation. The circuit has the advantages of capabilities of reducing hardware cost, decreasing calculation delay and improving calculation accuracy and the like.

Description

technical field [0001] The invention mainly relates to the field of digital signal processing, in particular to an FFT butterfly operation hardware implementation circuit supporting complex multiplication. Background technique [0002] In modern radar, communication, image processing and other fields, digital signal processing systems require a large number of high-speed, high-precision real-time FFT operations. At present, there are mainly two ways to realize FFT in the field of digital signal processing——DSP or FFT ASIC. The development time of the DSP programming implementation is short, but the power consumption is relatively large. In some special occasions, the required signal processing speed is extremely high, and higher requirements are placed on the performance, power consumption and efficiency of the FFT algorithm. It is difficult to meet the above requirements by using a general-purpose digital signal processor DSP chip. FFT ASIC has the advantages of fast spee...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/14
CPCG06F17/141
Inventor 雷元武高泽龙彭元喜刘宗林鲁建壮陈海燕孙书为陈小文吴虎成罗恒许邦建
Owner NAT UNIV OF DEFENSE TECH
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