A preparation method of virtual channel hole and three-dimensional memory

Abstract

The invention discloses a preparation method of a virtual channel hole and a three-dimensional memory. The preparation method includes the following steps: providing a substrate, on which a plurality of chip units are arranged, and between adjacent chip units. There is a scribe area, and a pattern alignment area is provided in the scribe area; the substrate is etched at different preset distances, and a plurality of openings are formed in the pattern alignment area; the surface of the pattern alignment area is removed The top stacked layer, exposing the fifth stacked layer; depositing an isolation material on the plurality of openings and the surface of the fifth stacked layer to form an isolation material layer; planarizing the isolation material layer and the fifth stacked layer Five stacked layers, so that the rest of the isolation material layer is flush with the surface of the fourth stacked layer; remove the fourth stacked layer to obtain multiple sets of regularly arranged grooves for the dummy trench Alignment of channel holes. The invention solves the problems of lengthy preparation steps of virtual channel holes, high manufacturing cost and poor alignment accuracy.

Description

technical field [0001] The invention belongs to the technical field of three-dimensional memory, and in particular relates to a preparation method of a virtual channel hole and a three-dimensional memory. Background technique [0002] Three-dimensional memory solves the limitations brought by two-dimensional or planar flash memory by vertically stacking multi-layer data storage units, and supports higher storage capacity in a smaller space, thereby effectively reducing costs and energy consumption. The control gate of the three-dimensional memory in the related art is usually formed by a gate-last process. The so-called gate-last process is a process in which the initially formed stacked layer contains several sacrificial layers arranged at intervals, and the sacrificial layer is removed in the subsequent process, and a polar dielectric (such as metal or polysilicon, etc.) is filled in the original space of the sacrificial layer. In the process of forming the control gate o...

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