Preparation method of virtual channel hole and three-dimensional memory

Abstract

The invention discloses a preparation method of a virtual channel hole and a three-dimensional memory, and the preparation method comprises the following steps: providing a substrate, the substrate is provided with a plurality of chip units, a cutting channel region is arranged between the adjacent chip units, and a pattern alignment region is arranged in the cutting channel region; etching the substrate at intervals of different preset distances, and forming a plurality of openings in the pattern alignment region; removing the top overlay layer on the surface of the pattern alignment region to expose the fifth overlay layer; depositing an isolation material on the plurality of openings and the surface of the fifth stacking layer to form an isolation material layer; performing planarization processing on the isolation material layer and the fifth stacking layer to enable the rest of the isolation material layer to be flush with the surface of the fourth stacking layer; and removing the fourth stacked layer to obtain a plurality of groups of regularly arranged grooves for alignment of the virtual channel holes. According to the invention, the problems of tedious preparation steps, high manufacturing cost and poor alignment precision of the virtual channel hole are solved.

Description

technical field [0001] The invention belongs to the technical field of three-dimensional memory, and in particular relates to a preparation method of a virtual channel hole and a three-dimensional memory. Background technique [0002] Three-dimensional memory solves the limitations brought by two-dimensional or planar flash memory by vertically stacking multi-layer data storage units, and supports higher storage capacity in a smaller space, thereby effectively reducing costs and energy consumption. The control gate of the three-dimensional memory in the related art is usually formed by a gate-last process. The so-called gate-last process is a process in which the initially formed stacked layer contains several sacrificial layers arranged at intervals, and the sacrificial layer is removed in the subsequent process, and a polar dielectric (such as metal or polysilicon, etc.) is filled in the original space of the sacrificial layer. In the process of forming the control gate o...

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