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119results about How to "Reduce craft production cost" patented technology

Method for preparing graphene through carrying out ultrasonic stripping on graphite

The invention belongs to the technical field of functional material preparation, and relates to a novel method for preparing graphene through carrying out ultrasonic stripping on graphite. The method comprises the following steps: uniformly mixing graphite powder and an intercalator in certain proportion in an organic solvent, carrying out stripping on the obtained mixture a certain time by using an ultrasonic water bath, carrying out centrifugal separation on the obtained object, and filtering the obtained product so as to obtain a graphene material. In the traditional process for preparing graphene through ultrasonic stripping, in the invention, a series of compounds such as naphthalene and the like are taken as an intercalator for preparing graphene. Compared with the prior art, the graphene prepared by using the method disclosed by the invention has the advantages of high quality, excellent performances, less defects, low impurity content, and the like; and especially the method is a physical process, thereby ensuring the perfect performances of the graphene. In addition, the method disclosed by the invention has the advantages of simpleness, easiness for operation, low preparation cost of products, high concentration of synthesized graphene dispersion liquid, and uneasiness for gathering, and has a good application prospect in the photoelectric field of graphene materials.
Owner:BOHAI UNIV

In-memory computing bit unit and in-memory computing device

The invention relates to an in-memory calculation bit unit and an in-memory calculation device, the in-memory calculation bit unit comprises a four-tube storage unit and a four-tube calculation unit,the four-tube calculation unit comprises a transistor T5, a transistor T6, a transistor T7 and a transistor T8; the drain electrode of the transistor T7 is connected with a pre-storage line A, the grid electrode of the transistor T7 is connected with a calculation word line, the source electrode of the transistor T7 is connected with the drain electrode of the transistor T5, the grid electrode ofthe transistor T5 is connected with the four-tube storage unit, the source electrode of the transistor T5 is connected with the source electrode of the transistor T6, and the grid electrode of the transistor T6 is connected with the four-tube storage unit; the drain electrode of the transistor T6 is connected with the drain electrode of the transistor T8, the grid electrode of the transistor T8 isconnected with the inverse calculation word line, and the source electrode of the transistor T8 is connected with the pre-storage line B; and the source electrode of the transistor T5 and the sourceelectrode of the transistor T6 are connected with a read bit line RBL. When the weight value is designed to be 0, the retention state is directly adopted, and the calculation process is accelerated.
Owner:中科南京智能技术研究院

Circuit converting high-voltage power supply into low-voltage power supply for enabling zero switching current of chip

The invention discloses a circuit converting a high-voltage power supply into a low-voltage power supply for enabling zero switching current of a chip. The circuit comprises an enabling control circuit, a high-voltage PMOS (P-channel Metal Oxide Semiconductor) tube proportion current mirror, a diode series connection network and a current amplifying and outputting circuit. According to the circuit disclosed by the invention, the low-voltage power supply which is converted from the high-voltage power supply and is required by a chip enabling module is realized by directly adopting a general device in a high-voltage process without a special device. The invention has the technical characteristics that: in the circuit disclosed by the invention, the high-voltage power supply is converted into the low-voltage power supply without a traditional architecture consuming quiescent current or the special device; the same function is achieved by adopting the most general device in the high-voltage process, so that the manufacturing cost of the process can be reduced; meanwhile, the quiescent current can be ensured to be zero when the chip is positioned in an enabling switching state; in addition, a low-voltage output power supply has basically no fluctuation along with the change of the high-voltage power supply; and stable voltage output and safety and reliability for work are achieved.
Owner:WUXI CHIPOWN MICROELECTRONICS

Manufacturing method of top gate type thin film transistor and top gate type thin film transistor

The present invention provides a manufacturing method of a top gate type thin film transistor and a top gate type thin film transistor. The manufacturing method of the top gate type thin film transistor comprises the steps of: forming a first insulation layer and a second insulation layer on a substrate in order; employing a first photomask to form a first via hole and a second via hole which arearranged on the second insulation layer at intervals; forming a penetrating groove below the first via hole and the second via hole on the first insulation layer, wherein the penetrating groove is configured to communicate the first via hole with the second via hole, and the penetrating groove, the first via hole and the second via hole commonly form a vertical U-shaped groove; filling and formingan active layer in the vertical U-shaped groove; and employing a second photomask to form a source electrode, a drain electrode and a grid electrode on the second insulation layer. The manufacturingmethod of the top gate type thin film transistor and the top gate type thin film transistor simplifies the structure of the top gate type thin film transistor and reduces the number of photomask manufacture procedures, two photomasks are only used to complete manufacturing of the top gate type thin film transistor with the vertical U-shaped groove, and therefore, the process manufacturing cost issaved.
Owner:SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD

High-strength and high-toughness silicon carbide ceramic bearing plate, manufacturing method and application thereof

The invention discloses a high-strength and high-toughness silicon carbide ceramic bearing plate, a manufacturing method and application thereof. The silicon carbide ceramic bearing plate is preparedfrom the following materials in parts by mass: 70-95 parts of silicon carbide, 2-10 parts of silicon carbide whiskers, 1 to 15 parts of tungsten carbide, 0.5 to 5 parts of boron carbide, 1 to 10 partsof a binder and 0.5 to 10 parts of a lubricant. The manufacturing method comprises burdening, mixing, pulping, spray drying, isostatic pressing, sintering and finish machining. The silicon carbide ceramic bearing plate is applied to the assembly of chemical-mechanical polishing devices. According to the silicon carbide ceramic bearing plate made by the manufacturing method, the strength and toughness are greatly superior to a common corundum ceramic bearing plate at present; a ceramic bearing plate with the same size can be reduced by 1/3 in thickness; the ceramic bearing plate is applied tothe chemical-mechanical polishing devices, the stability in the polishing process is greatly improved, the reliability in the operation process is greatly increased, the service life of the ceramic bearing plate is greatly prolonged, and the process manufacturing cost is reduced.
Owner:NANTONG SANZER PRECISION CERAMICS CO LTD

Induction remelting machine tool

InactiveCN101724840AFast and uniform heatingImprove the surface hardness valueMetallic material coating processesEngineeringHigh surface
The invention provides an induction remelting machine tool for induction remelting of an alloy (ceramics) powder coating and a metallic base material.The machine tool body is provided with a main spindle box and a tail bracket which are arranged in opposite direction, assist in clamping workpieces and drive the workpieces to rotate; the workpieces clamped by the main spindle box and the tail bracket are sleeved into an inductor which can heat the workpieces, the inductor is arranged on a carriage which can drag the inductor to do reciprocating motion.The machine tool of the invention solves the defects in the prior art that remelting temperature control is not accurate, the workpieces are not preheated and heated evenly, the remelted crystal grains are coarse, the remelting efficiency is low, the production quality is not stable and the like. The machine tool of the invention has the advantages of quick and even remelting temperature rise, small deformation of workpieces, high quality remelting, fine crystal grains in an induction remelting coating, high surface hardness value, and superiority of the corrosion resistance and abrasive resistance of the coating to the corrosion resistance and abrasive resistance of oxyacetylene flame remelting coating with more coarse crystal grains, low cost in technology investment and production and the like.
Owner:王洪刚

Preparing method for copper oxide spherical hierarchical structure material

The invention belongs to the technical field of functional material preparation and relates to a preparing method for a copper oxide spherical hierarchical structure material. A mineralizing agent is added into an oxalic acid aqueous solution, then a soluble copper salt aqueous solution is dropwise added, and a reaction is carried out under the constant temperature and stirring conditions until precursor precipitate is generated; filtering, washing, drying and roasting are carried out, and the copper oxide spherical hierarchical structure material is obtained. The copper oxide spherical hierarchical structure material is formed through assembling of a large quantity of copper oxide nanoparticles. The dimension of spheres ranges from 1 mm to 2 mm, the dimension of the copper oxide nanoparticles ranges from 40 nm to 60 nm, and the dimension of pore canals of the copper oxide nanoparticles ranges from 10 nm to 30 nm. The technology is low in preparing cost, operation is easy to control, high production efficiency is achieved, and industrial mass production can be achieved. The copper oxide spherical hierarchical structure material prepared with the method has high catalytic activity when serving as a visible light catalytic material and has wide application prospects in the fields such as dye wastewater and indoor harmful gas degradation and photocatalystic disinfection.
Owner:BOHAI UNIV

Pinion-and-rack type power steering gear valve element assembly

The invention relates to a pinion-and-rack type power steering gear valve element assembly and belongs to the technical field of automobile steering gears. The steering gear valve element assembly is composed of a pinion shaft, a valve sleeve, an input shaft and a torsion bar. The input shaft is installed on the pinion shaft through the valve sleeve. The torsion bar is installed in an inner hole of the input shaft through a cylindrical pin. A blind groove A and a blind groove B are correspondingly formed between the valve sleeve and the torsion bar. An oil inlet A and an oil outlet B are formed in the valve sleeve. The oil inlet A and the oil outlet B are communicated with the blind groove A and the blind groove B respectively. Compared with an existing power steering gear valve element assembly, needle bearings used for supporting the input shaft and the torsion bar are omitted, so that the product structure is optimized, the quality of the process that the torsion bar is pressed through the pinion shaft and the bouncing quality after a pin is punched into the valve element assembly are improved, the production and manufacturing cost is reduced to a certain degree, the output is improved, the quality control in the process is stable, and the requirements for automobile loading and quality are met.
Owner:荆州恒隆汽车零部件制造有限公司

Capacitance-free DRAM (Dynamic Random Access Memory) unit structure and manufacturing method

The invention relates to a capacitance-free DRAM (Dynamic Random Access Memory) unit structure and a manufacturing method. The capacitance-free DRAM unit structure comprises a semiconductor substrate, a first isolation layer, a lower source-drain layer, a lower active region, a lower gate dielectric layer, a lower gate electrode layer, a second isolation layer, an upper source-drain layer, an upper active region layer, an upper gate dielectric layer and an upper gate electrode layer which are sequentially stacked from bottom to top, the lower source drain layer comprises a lower source electrode and a lower drain electrode which are separated by a first groove, and the bottom of the first groove is in contact with the first isolation layer; the upper source drain layer comprises an upper source electrode and an upper drain electrode which are separated by a second groove, and the bottom of the second groove is in contact with the second isolation layer; the lower gate electrode layer and the upper source drain layer are electrically connected through a contact hole arranged in the second isolation layer. According to the DRAM unit structure, the upper transistor and the lower transistor are completely overlapped, the unit area is saved, the integration density is improved, multiplexing of a gate electrode photoetching plate can be achieved, and the manufacturing cost is reduced.
Owner:INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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