The present invention relates to a 6T unit-based storage unit. The storage unit comprises a PMOS transistor T1, a PMOS transistor T2, an NMOS transistor T3, an NMOS transistor T4, an NMOS transistor T5, an NMOS transistor T6, an NMOS transistor T7, an NMOS transistor T8, an NMOS transistor T9, an NMOS transistor T10, a capacitor C_U, a capacitor C_D, a word line WL, a bit line BL, a bit line BLB,a bit reading line RBL_L, a computing word line CWL_U, a differential signal end CWLB_U, a computing word line CWL_D, a differential signal end CWLB_D and a bit reading line RBL_R. The circuit is conducted only when the voltages at the two ends of the capacitor are changed in the calculation process, the power consumption is saved through a capacitance coupling calculation mode, and the energy efficiency is improved.