Capacitance-free DRAM (Dynamic Random Access Memory) unit structure and manufacturing method

Abstract

The invention relates to a capacitance-free DRAM (Dynamic Random Access Memory) unit structure and a manufacturing method. The capacitance-free DRAM unit structure comprises a semiconductor substrate, a first isolation layer, a lower source-drain layer, a lower active region, a lower gate dielectric layer, a lower gate electrode layer, a second isolation layer, an upper source-drain layer, an upper active region layer, an upper gate dielectric layer and an upper gate electrode layer which are sequentially stacked from bottom to top, the lower source drain layer comprises a lower source electrode and a lower drain electrode which are separated by a first groove, and the bottom of the first groove is in contact with the first isolation layer; the upper source drain layer comprises an upper source electrode and an upper drain electrode which are separated by a second groove, and the bottom of the second groove is in contact with the second isolation layer; the lower gate electrode layer and the upper source drain layer are electrically connected through a contact hole arranged in the second isolation layer. According to the DRAM unit structure, the upper transistor and the lower transistor are completely overlapped, the unit area is saved, the integration density is improved, multiplexing of a gate electrode photoetching plate can be achieved, and the manufacturing cost is reduced.

Description

technical field [0001] The present invention relates to the field of transistors, in particular to a structure and a manufacturing method of a capacitorless DRAM cell. Background technique [0002] The traditional DRAM (Dynamic Random Access Memory) unit consists of a transistor and a capacitor, but with the increase of integration, the capacitor structure continues to shrink, the charge storage continues to decrease, the leakage is too fast, and the DRAM is about to reach the refresh frequency limit. . [0003] Therefore, two oxide semiconductors IGZO (Indium Gallium Zinc Oxide InGaZnO 4 ) 2T0C (2transistor 0capacitor dual transistor no capacitor) DRAM cell with thin film transistor, such as figure 1 As shown, the drain of one transistor is connected to the gate of the other transistor, using the gate capacitance to store charge and changing the transistor transconductance to store information. [0004] In recent years, 2T0C memories with indium gallium zinc oxide (Indiu...

AI Technical Summary

Problems solved by technology

However, the existing 2T0C DRAM cells based on IGZO TFT generally use two horizontal channel TFTs connected on the same plane, occupying a large area and low integration density

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