Board-level fan-out chip packaging device and preparation method thereof

A chip packaging, fan-out technology, used in semiconductor/solid-state device manufacturing, electrical solid-state devices, semiconductor devices, etc., can solve problems such as development and cost reduction, and achieve the effect of improving performance, improving heat dissipation, and eliminating dependencies

Active Publication Date: 2015-12-09
广东佛智芯微电子技术研究有限公司
View PDF10 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, at present, many placement machines (DB equipment) cannot meet the needs of increasing board size and higher precision requirements, which limits the further development of this technology and the reduction of costs

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Board-level fan-out chip packaging device and preparation method thereof
  • Board-level fan-out chip packaging device and preparation method thereof
  • Board-level fan-out chip packaging device and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

preparation example Construction

[0038] Therefore, the method for manufacturing a board-level fan-out chip package device provided according to an embodiment of the present invention includes: providing a carrier board on which a recess is provided, and the size of the recess is suitable for accommodating the chip; The back-mount and the recess of the carrier board; the dielectric layer is arranged on the recessed side of the carrier board, over the carrier board and the chip; and by pressing the carrier board and the dielectric layer, the material of the dielectric layer can be filled to the The recess of the carrier board and the gap between the chips.

[0039] The structure of the chip packaging device 10 according to the embodiment of the present invention has been embodied in the above description of the process flow, such as Figure 3-Figure 9 its cross-section shown. like Figure 4 As shown, the board-level fan-out chip package device 1004 includes: a carrier board on which recesses are provided, the...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The embodiment of the invention relates to a board-level fan-out chip packaging device and a preparation method thereof. A recess is formed in one side of a bearing board used for bearing a chip, the size of the recess is matched with the size of the back side of the chip, and the chip is mounted in the recess. When the chip is mounted to the bearing board, the recess in the bearing board exactly accommodates the back side of the chip, so that the chip to be packaged is easy and convenient to put in place. According to the invention, the dependence of fan-out packaging on the format of a chip mounter and chip mounting precision is eliminated, so that the development of the large-format fan-out chip packaging technology is facilitated.

Description

technical field [0001] The present invention relates to the technical field of chip packaging, and more particularly, to a fan-out chip packaging device and a preparation method thereof. Background technique [0002] With the continuous development of information technology and semiconductor technology, electronic devices such as mobile phones, PADs, and smart watches are gradually becoming lighter and more functionally integrated. This requires higher and higher integration levels of chips, which in turn brings unprecedented challenges to chip packaging. Growing interconnect pitch mismatch, adding various chips with different functions, and reducing package size in the same footprint to increase battery size and extend life have all opened the window for innovative embedded packaging technologies. [0003] Benefiting from the development of 3D through-silicon via (TSV) technology, fan-out wafer level packaging (FOWLP) is currently considered to be the most suitable for the...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/13H01L23/367H01L23/373H01L21/58H01L21/68
CPCH01L24/19H01L2224/04105H01L2224/12105H01L2224/19H01L2224/20H01L2224/32225H01L2224/32245H01L2224/73267H01L2224/92244H01L2924/15156H01L2924/00012
Inventor 郭学平
Owner 广东佛智芯微电子技术研究有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap