6T unit-based storage unit, storage array and in-memory computing device

Abstract

The present invention relates to a 6T unit-based storage unit. The storage unit comprises a PMOS transistor T1, a PMOS transistor T2, an NMOS transistor T3, an NMOS transistor T4, an NMOS transistor T5, an NMOS transistor T6, an NMOS transistor T7, an NMOS transistor T8, an NMOS transistor T9, an NMOS transistor T10, a capacitor C_U, a capacitor C_D, a word line WL, a bit line BL, a bit line BLB,a bit reading line RBL_L, a computing word line CWL_U, a differential signal end CWLB_U, a computing word line CWL_D, a differential signal end CWLB_D and a bit reading line RBL_R. The circuit is conducted only when the voltages at the two ends of the capacitor are changed in the calculation process, the power consumption is saved through a capacitance coupling calculation mode, and the energy efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of in-memory computing, in particular to a storage unit based on a 6T unit, a storage array and an in-memory computing device. Background technique [0002] Deep neural networks (DNNs) and convolutional neural networks (CNNs) have achieved unprecedented improvements in the accuracy of large-scale recognition tasks. In order to solve the problem of algorithm complexity and memory access limitation, in recent algorithms, weights and neuron activations are binarized as +1 or −1, so that the multiplication between weights and input activations becomes an XNOR operation, and the accumulation of XNOR operations becomes the number of bits of these XNOR results. [0003] However, when performing XNOR operations, the traditional on-chip static random access memory SRAM needs to be accessed row by row, and the throughput is low. [0004] The traditional calculation method of single-bit input multiplied by single-bit...

AI Technical Summary

Problems solved by technology

[0004] The traditional calculation method of single-bit input multiplied by single-bit weight is inefficient, and has no comparative advantage in calculation throughput; the use of 8T structure for weight storage will increase the process cost; consumption problem

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