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Chip structure and operation method thereof

A chip structure and action technology, applied in the direction of instruments, electrical digital data processing, digital data protection, etc., can solve problems such as data leakage, unprepared probe detection bus, etc., and achieve the effect of improving security

Pending Publication Date: 2021-07-27
青芯半导体科技(上海)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The purpose of the present invention is to provide a chip structure and its operation method to solve the problem of data leakage caused by the unprepared probe detection bus of the existing security chip

Method used

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  • Chip structure and operation method thereof
  • Chip structure and operation method thereof
  • Chip structure and operation method thereof

Examples

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Embodiment Construction

[0074] In the present invention, each embodiment is only intended to illustrate the solutions of the present invention, and should not be construed as limiting.

[0075] In the present invention, unless otherwise specified, the quantifiers "a" and "an" do not exclude the scene of multiple elements.

[0076] It should also be pointed out here that in the embodiments of the present invention, for the sake of clarity and simplicity, only a part of parts or components may be shown, but those skilled in the art can understand that under the teaching of the present invention, specific The scene needs to add the required parts or components. In addition, unless otherwise stated, features in different embodiments of the present invention can be combined with each other. For example, a feature in the second embodiment may be used to replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment also falls within the scope of ...

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PUM

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Abstract

The invention provides a chip structure and an operation method thereof. The operation method comprises the following steps: at least one bus master device initiates a read command and / or a write command, provides the read command and / or the write command to a bus, and receives write data and / or read data; the at least one bus transmits the read command and / or the write command to the bus slave device and transmits the write data and / or the read data to the bus master device; the at least one bus slave device receives the read command and / or the write command, generates write data and / or read data according to the read command and / or the write command, and provides the write data and / or the read data to the bus; at least one first encryption and decryption module is connected between any bus master device and any bus, and is used for encrypting and / or decrypting commands and data transmitted between the bus master device and the bus; at least one second encryption and decryption module is connected between any bus slave device and any bus, and encrypts and / or decrypts commands and data transmitted between the bus slave device and the bus.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a chip structure and an operation method thereof. Background technique [0002] In recent years, with the development of cloud computing, Internet of Things, mobile computing and other technologies and the continuous expansion of application fields, the leading role of modern information technology in social life has become more and more prominent. At the same time, more and more attention and research are being paid to physical attacks against security chips. Sensitive data, such as keys and user privacy-related information, are often stored in security chips, and physical attacks against security chips are becoming more and more abundant. Through various means to obtain these sensitive information. A physical attack will first remove the chip package, and then peel off the chip layer by layer through physical or chemical means. For all types of memory, an attacker...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/60G06F21/72G06F21/85
CPCG06F21/602G06F21/72G06F21/85
Inventor 江国范孙向向
Owner 青芯半导体科技(上海)有限公司
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