A data acceleration calculation method and related device

Abstract

The present application discloses a data acceleration calculation method, including: an acceleration device acquires calculation acceleration management and control information from the host memory; wherein, the calculation acceleration management and control information includes input parameter address information and calculation configuration information; Obtain the parameters to be calculated; control the calculation unit to perform calculation operations on the parameters to be calculated based on the calculation configuration information, and obtain calculation results. The acceleration device actively obtains the acceleration control information from the host memory through the acceleration device, and then based on the acceleration control information, the acceleration device actively obtains the corresponding data required for acceleration, and automatically executes the accelerated computing operation, instead of the host constantly actively sending data to the acceleration device The calculation of the data is accelerated, which improves the efficiency of the host side and reduces the performance pressure on the host side. The application also discloses a data acceleration computing device, acceleration equipment, server, and computer-readable storage medium, which have the above beneficial effects.

Description

technical field [0001] The present application relates to the technical field of data processing, and in particular to a data acceleration computing method, a data acceleration computing device, an acceleration device, a server, and a computer-readable storage medium. Background technique [0002] With the continuous development of information technology, the acceleration framework represented by OpenCL (Open Computing Language, Open Computing Language) has been paid more and more attention. At the same time, more and more data centers have begun to use FPGA (Field Programmable Gate Array, Field Programmable Gate Array ) for acceleration, and large-scale data centers have deployed FPGA computing cards on a large scale to provide powerful computing capabilities and sufficient flexibility for various acceleration applications. [0003] In related technologies, the CPU (central processing unit, central processing unit) software layer of the acceleration platform first initiates...

AI Technical Summary

Problems solved by technology

However, the host will generate multiple register reads and writes and DMA operations, the number of read and write responses is too many, the efficiency is low, and the device handle of the FPGA accelerator is occupied, which puts pressure on the host's multi-thread scheduling

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