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Embedded parallel computing system and parallel computing method adopting same

A parallel computing and embedded technology, applied in the field of data processing, can solve problems such as difficult load balancing of multiple different tasks, difficult application of embedded fields, waste of computing resources, etc., to avoid the barrel effect and reduce power consumption , the effect of improving computational efficiency

Active Publication Date: 2015-11-11
SHANDONG HUAYU AEROSPACE TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this way, for each project, tasks need to be re-divided according to requirements, and it is difficult to load balance multiple different tasks, which will lead to barrel effect and waste computing resources
In the traditional multi-DSP system that uses task pipeline, once a certain DSP fails, it will lead to the paralysis of the whole system
[0004] However, traditional parallel computing systems mostly use Ethernet-based large-scale cluster systems, which are bulky, high power consumption, and low communication bandwidth, making it difficult to apply to the embedded field.

Method used

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  • Embedded parallel computing system and parallel computing method adopting same
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  • Embedded parallel computing system and parallel computing method adopting same

Examples

Experimental program
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Embodiment 1

[0020] Embodiment 1. An embedded parallel computing system. The following combination figure 1 with figure 2 The system provided in this embodiment will be described in detail.

[0021] see figure 1 , the system provided in this embodiment includes a data input module, a plurality of identical chassis and a data output module. Also, see figure 2 , each of the chassis includes two switching modules, a plurality of computing modules, a backplane and a power management module; each of the switching modules includes a fiber converter, a SRIO (SerialRapidI / O) switching chip and a GbE ( GigabitEthernet, Gigabit Ethernet) switching chip, each of the computing modules includes two multi-core DSPs (Digital Signal Processing, digital signal processing), an SRIO switching chip and an FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array). The SRIO switching chip in each of the switching modules is connected to the SRIO switching chip in each of the computing mod...

Embodiment 2

[0026] Embodiment 2, a parallel computing method. The following combination image 3 with Figure 4 The method provided in this embodiment is described in detail.

[0027] see image 3 , the method provided in this embodiment includes: S1. The external input interface inputs data to be processed to the Master through the data input module.

[0028]Specifically, the process of determining the Master from all DSPs in the embedded parallel computing system is: after power-on, all DSPs broadcast their own unique ID numbers to other DSPs through GbE, and when the broadcast is received, each DSP The ID numbers of all DSPs are stored; each DSP sorts the ID numbers of all DSPs according to predetermined rules, and the DSP corresponding to the first ID number is regarded as the Master of all DSPs, and the other DSPs are regarded as Slaves.

[0029] It should be noted that the external input interface is usually CameraLink, LVDS, TLK2711, 10GbE, InfiniBand or a custom high-speed int...

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Abstract

The invention discloses an embedded parallel computing system and a parallel computing method adopting the same. The system comprises a data input module, a plurality of identical cases and a data output module, wherein each case comprises two exchange modules, a plurality of computing modules, a bottom plate and a power supply management module; each exchange module comprises a fiber converter, an SRIO (Serial Rapid I / O) exchange chip and a GbE (Gigabit Ethernet) exchange chip; and each computing module comprises two multicore DSPs (Digital Signal Processors), an SRIO exchange chip and an FPGA (Field Programmable Gate Array). Through the invention, the embedded parallel computing system having the advantages of high operation capability, high reliability, modularization, expansibility, miniaturization, low power consumption and high bandwidth can be provided. Moreover, through the system, computing resources can be automatically allocated in a balanced way, and a standard parallel computing program interface is provided.

Description

technical field [0001] The invention relates to the technical field of data processing, in particular to an embedded parallel computing system and a parallel computing method using the same. Background technique [0002] At present, in the field of embedded computing, especially in the field of space starboard computing systems, the structure of FPGA plus single-chip single-core DSP is mostly used. Its computing power per unit time is low, and it is difficult to meet the increasing data volume and complex algorithms. increasing demand. [0003] In some communication or radar fields, some systems adopt a structure in which multiple single-core DSPs coordinate processing, but run different tasks on each DSP, and process data in a task pipeline manner. In this way, for each project, tasks need to be re-divided according to requirements, and it is difficult to load balance multiple different tasks, which will lead to barrel effect and waste computing resources. In the traditio...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
Inventor 徐明道栾丽林巍刁奇宋磊刘建文
Owner SHANDONG HUAYU AEROSPACE TECH CO LTD