Data acceleration calculation method and related device

Abstract

The invention discloses a data acceleration calculation method. The method comprises: an acceleration device obtaining calculation acceleration management and control information from a host memory; wherein the calculation acceleration management and control information comprises input parameter address information and calculation configuration information; obtaining a to-be-calculated parameter from a host memory based on the input parameter address information; and controlling the calculation unit to execute calculation operation on the to-be-calculated parameter based on the calculation configuration information to obtain a calculation result. The acceleration control information is actively acquired from the host memory through the acceleration device, then the acceleration device actively acquires the corresponding data required for acceleration based on the acceleration control information, and the acceleration calculation operation is automatically executed instead of continuously and actively sending the data to the acceleration device by the host end to perform calculation acceleration. The efficiency of the host end is improved, and the performance pressure on the host end is reduced. The invention further discloses a data acceleration calculation device, acceleration equipment, a server and a computer readable storage medium, which have the above beneficial effects.

Description

technical field [0001] The present application relates to the technical field of data processing, and in particular to a data acceleration computing method, a data acceleration computing device, an acceleration device, a server, and a computer-readable storage medium. Background technique [0002] With the continuous development of information technology, the acceleration framework represented by OpenCL (Open Computing Language, Open Computing Language) has been paid more and more attention. At the same time, more and more data centers have begun to use FPGA (Field Programmable Gate Array, Field Programmable Gate Array ) for acceleration, and large-scale data centers have deployed FPGA computing cards on a large scale to provide powerful computing capabilities and sufficient flexibility for various acceleration applications. [0003] In related technologies, the CPU (central processing unit, central processing unit) software layer of the acceleration platform first initiates...

AI Technical Summary

Problems solved by technology

However, the host will generate multiple register reads and writes and DMA operations, the number of read and write responses is too many, the efficiency is low, and the device handle of the FPGA accelerator is occupied, which puts pressure on the host's multi-thread scheduling

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