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PIP capacitor structure, manufacturing method thereof and semiconductor device

A technology of capacitor structure and fabrication method, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of easy diffusion, short service life, TDDB test failure, etc., so as to reduce thickness loss and improve shock resistance. The effect of wearability

Pending Publication Date: 2022-04-12
WUHAN XINXIN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the floating gate layer is relatively thin , the Co in the contact layer is easy to diffuse to the interface of the tunnel oxide layer, causing the TDDB test to fail. Correspondingly, the breakdown resistance of the PIP capacitor structure is weak and the service life is not long.

Method used

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  • PIP capacitor structure, manufacturing method thereof and semiconductor device
  • PIP capacitor structure, manufacturing method thereof and semiconductor device
  • PIP capacitor structure, manufacturing method thereof and semiconductor device

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Embodiment Construction

[0056]The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

[0057] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, It is not intended to indicate or imply that the device or element referred to must have a particular orient...

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Abstract

The invention provides a PIP capacitor structure and a manufacturing method thereof, and a semiconductor device. The PIP capacitor structure comprises a substrate; the tunneling oxide layer is formed on the substrate; the floating gate layer is formed on the tunneling oxide layer; the dielectric layer is formed on the floating gate layer; the control gate layer is formed on the dielectric layer, the dielectric layer and the control gate layer are provided with at least one window, and part of the floating gate layer is exposed out of the window; and at least one height adjusting structure. And the height adjusting structure penetrates through the floating gate layer, the tunneling oxide layer and part of the substrate. According to the PIP capacitor structure, the manufacturing method thereof and the semiconductor device, the breakdown resistance of the PIP capacitor structure can be improved, and the service life of the PIP capacitor structure can be prolonged.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a PIP capacitor structure, a manufacturing method thereof, and a semiconductor device. Background technique [0002] Capacitors are widely used in integrated circuits. Capacitors can perform various functions such as coupling, filtering, and compensation. In the chip, the lower voltage of the capacitor can be raised to a higher voltage through the charge pump circuit to meet the electrical needs of the product. The PIP (Poly-Insulator-Poly) capacitor structure is a commonly used capacitor structure and is used in various chips. Generally speaking, the PIP capacitor structure can be fabricated by the stacked gate structure of floating gate transistors. The stacked gate structure includes a tunnel oxide layer, a floating gate layer formed on the tunnel oxide layer, a dielectric layer formed on the floating gate layer, and a control gate layer formed on the diel...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/788H01L29/92H01L21/336H01L21/329
Inventor 耿武千
Owner WUHAN XINXIN SEMICON MFG CO LTD