Testing component including work line of memory and capacitor overlaped and offset as well as its testing method

A technology of memory words and test elements, applied in the direction of semiconductor/solid-state device testing/measurement, etc., can solve the problems such as the decrease of the qualification rate of the manufacturing process, the invalidation of the memory cells, and the influence of the size of the doping area.

CN1248301CInactive Publication Date: 2006-03-29NAN YA TECH
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Publication Date
2006-03-29
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention relates to testing component and method, especially a testing component in slotting track for testing an offset of overlapped DRAM word line structure with deep groove capacitor. The said capacitor possesses an embedding plate, a rectangle word line covering part of deep groove capacitor, first and second across word lines, first and second doping areas, first and second as well as third plugs. The first plug is coupled to first doping area; second plug is coupled to second doping area; the third plug is coupled to the embedding plate.
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Description

technical field

[0001] The present invention relates to a test element (test key) and a method, in particular to a test element for detecting the overlapping offset of a word line structure of a dynamic random access memory and a deep trench capacitor (deep trench capacitor), and a test element for detecting the trench capacitor and active Area (active area) misalignment (misalignment) test components. Background technique

[0002] The trench capacitor is a common capacitor structure in dynamic random access memory (DRAM), which is formed in the semiconductor silicon substrate, and its depth can be increased by increasing the depth of the trench capacitor in the semiconductor silicon substrate. surface area to increase its capacitance.

[0003] figure 1 is a layout diagram of a conventional trench capacitor. The trench capacitor 10 is disposed under the passing wordline. The transistor 14 is electrically coupled to the storage node 16 of the trench capacitor 10 via the d...

Examples

Embodiment Construction

[0016] Please refer to image 3 as well as Figure 4a , Figure 4b , to illustrate an embodiment of the present invention. in image 3 It is a layout diagram of test elements used to detect the overlapping offset of word line structure and deep trench capacitors of a dynamic random access memory in the present invention, wherein the test elements are arranged in the dicing lanes of the chip. Figure 4a it's for image 3 section along the line segment B-B', while Figure 4b it's for image 3 Sectional view along line segment C-C'.

[0017] First, a trench capacitor 110 is disposed on the scribe line region 160 of a chip 100 . The trench capacitor 110 includes a storage node 116, a buried plate 181 in the buried n-type well region NW, and a capacitor dielectric layer therebetween. The storage node 116 is electrically isolated from the doped p-type well region PW by a dielectric collar 126 .

[0018] Next, on the scribe area 160, a rectangular word line 12a, a first pass...