High-capacity cache memory

A high-speed buffer storage and high-speed buffering technology, applied in static memory, digital memory information, information storage and other directions, can solve the problems of low read and write data rate of hard disk ports, affecting high-speed interface bandwidth, long time interval of hard disk ports, etc. The effect of buffer memory capacity, small read and write access latency, and large access bandwidth

Active Publication Date: 2007-05-23
HUAWEI TECH CO LTD
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Problems solved by technology

However, the read and write data rate of the hard disk port is relatively small, the maximum bandwidth is hundreds of megabits per second, and the time interval for reading and writing of the hard disk port is relatively long, and the reading and writing interval is several milliseconds, which not only affects the bandwidth of the high-speed interface, but also affects the response of real-time data speed
Therefore, when the speed of the high-speed interface increases, especially after the speed of the interface reaches Gigabit, using the hard disk as a high-speed buffer cannot meet the requirements of users.

Method used

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Embodiment Construction

[0020] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described below in conjunction with the accompanying drawings.

[0021] Please refer to shown in Fig. 1, the high-capacity high-speed storage buffer of the present invention adds the Cache that is made up of double data rate synchronous dynamic random access memory stick array (DDRSDRAM DIMM Array, hereinafter referred to as DDR Array) between the high-speed interface chip and the data processing module A unit and a Cache controller unit implemented with a Field Programmable Gate Array (Field Programmable Gate Array, hereinafter referred to as FPGA). The data processing module can store data in the Cache unit composed of DDR Array, or read data from the Cache unit as needed, and the high-speed interface unit exchanges data with the Cache unit through the Cache controller.

[0022] DDR Array is symmetrically divided into 2 or 2 according ...

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Abstract

The invention of large-capacity high-speed cache memory comprises the high-speed cache memory controller and the high-speed cache memory units composed of DDR SDRAM array, and the address of the DDR SDRAM memory space changes in turn according array sequence. The invention uses DDR SDRAM memory array as a high-speed interface of cache memory, and provides greater access bandwidth and larger cache memory capacity for the high-speed interface, and also provides a relatively small delay for read and write access of the high-speed interface.

Description

technical field [0001] The invention relates to a large-capacity high-speed buffer memory used for high-speed interfaces, in particular to a large-capacity high-speed cache memory used for real-time transmission of large-capacity data in a computer system. Background technique [0002] In the current computer structure, in order to improve the data access speed of the processor, a cache memory (Cache) is usually set between the processor and the main memory. With the continuous improvement of computer processing speed and the continuous increase of users' requirements for data bandwidth, the transmission rate of port data is also getting higher and higher. When real-time large-capacity data transmission is required, especially when transmitting real-time video data for multiple users, the traditional method of adding a buffer in the interface chip can no longer meet the requirements of providing high-speed buffer memory for high-speed interfaces, so additional large capacity...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/10G11C8/16
Inventor 王曰孟
Owner HUAWEI TECH CO LTD
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