Low latency memory erase suspend operation

a memory erase and low latency technology, applied in the field of nonvolatile memory, can solve the problems of increasing die area and cost, affecting the performance of the memory cell, and unable to read operations on other memory cells sharing the same bit line with the over-erased memory cell, etc., and achieve the effect of increasing the threshold voltag

Active Publication Date: 2020-11-03
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach reduces leakage from over-erased memory cells with low latency, meeting the erase suspend command requirements while minimizing die area and cost, thus enhancing the operational efficiency of flash memory devices.

Problems solved by technology

Read operations on other memory cells sharing the same bit line with the over-erased memory cell can fail due to leakage current caused by the conductive over-erased memory cell.
However, the method for applying a negative voltage to reduce leakage from over-erased memory cells requires negative voltage pump circuits that can increase die area and cost.

Method used

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  • Low latency memory erase suspend operation
  • Low latency memory erase suspend operation
  • Low latency memory erase suspend operation

Examples

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Embodiment Construction

[0022]A detailed description of embodiments of the present technology is provided with reference to the Figures.

[0023]FIG. 1 is a simplified block diagram of an example memory 175. The memory 175 includes an array 160 of memory cells. The array 160 can include NOR flash memory cells, NAND flash memory cells, or other suitable charge storage nonvolatile memory cells.

[0024]An address decoder 161 is coupled to the array 160 via lines 162. Addresses are supplied on bus 165 to the address decoder 161. The address decoder 161 can include word line decoders, bit line decoders, and other suitable decoders that decode the supplied addresses and select corresponding memory cells in the array 160.

[0025]Bit lines in the array 160 are coupled via lines 164 to a page buffer 163, which in turn are coupled to other peripheral circuitry 174 via lines 173.

[0026]Peripheral circuitry includes circuits that are formed using logic circuits or analog circuits that are not part of the array 160, such as th...

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Abstract

A method for an erase operation on a nonvolatile memory array with low-latency erase suspend is described. The nonvolatile memory array includes a plurality of blocks of memory cells, each block including a plurality of sectors of memory cells. The method includes, in response to an erase command identifying a block in the plurality of blocks in the array, erasing the plurality of sectors in the identified block, and determining whether there are over-erased cells in each sector. The method includes recording the over-erased cells for the sector. The method also includes responsive to suspend before a soft program pulse for the sector, applying a correction pulse to the recorded cells.

Description

TECHNICAL FIELD[0001]This disclosure relates to nonvolatile memory.DESCRIPTION OF RELATED ART[0002]Flash memory is a class of nonvolatile integrated circuit memory technology. A memory cell of a flash memory device includes a charge storage structure such as a floating gate or a dielectric charge trapping layer. Data is stored in a memory cell of a flash memory device by controlling the amount of charge stored in the charge storage structure. The amount of stored charge sets a threshold voltage for the memory cell in the flash memory device that is associated with a value of the stored data.[0003]Data can be programmed into a flash memory cell by applying program voltage pulses to the flash memory cell, causing charge to be stored in the charge storage structure of the cell. Data can be erased from a flash memory cell by applying erase voltage pulses to the flash memory cell, causing charge to be removed from the charge storage structure of the cell.[0004]Sometimes after subjecting ...

Claims

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Application Information

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Patent Type & AuthorityPatents(United States)
IPC IPC(8): G11C16/34G11C16/16
CPCG11C16/3409G11C16/16G11C16/3445
InventorHSU, WEN-MINGKUO, NAI-PINGHUNG, CHUN-HSIUNG
OwnerMACRONIX INT CO LTD