Semiconductor device including a wiring board with a three-dimensional wiring pattern

Inactive Publication Date: 2004-10-28
SHIRAISHI TSUKASA +3
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0010] The present inventors have found that it becomes possible to produce semiconductor devices of smaller size while maintaining a high operating speed of the semiconductor elements by mounting general-purpose semiconductor elements so that they oppose each other via a multi-layer wiring board, in which both sides of the multi-layer wiring board has a three-dimensional wiring layout employing inner via holes for connecting electrodes of the semiconductor elements with each other. Particularly, the semiconductor device can be produced without making the wiring longer even when the semiconductor element has an area array type electrode arrangement by employing the three-dimensional wiring as described above. Thus, the present invention has been completed.
[0046] Also by connecting the bypass capacitors and the semiconductor elements by the three-dimensional wiring comprising the inner via holes, it becomes possible to reduce the wiring length and reduce the noise generated in the semiconductor device.

Problems solved by technology

In practice, however, it is difficult to make a single semiconductor element having all necessary functions due to limitations related to semiconductor material, production process, design rule and other factors, and it is often necessary to use a plurality of semiconductor elements.
Consequently, it is impossible to design the semiconductor elements separately.
Also because the positions of the electrodes 2, 4 of the first and the second semiconductor elements are restricted, it becomes difficult to reduce the size of the semiconductor device in some cases, eventually resulting in lower production yield.

Method used

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  • Semiconductor device including a wiring board with a three-dimensional wiring pattern
  • Semiconductor device including a wiring board with a three-dimensional wiring pattern
  • Semiconductor device including a wiring board with a three-dimensional wiring pattern

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Experimental program
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first embodiment

[0067] FIGS. 1A, 1B show a semiconductor device according to the present invention. This semiconductor device has two semiconductor elements on one side and one semiconductor element on the other side.

[0068] FIG. 1A is a perspective view of the semiconductor device and FIG. 1B is a cross sectional view taken along lines I-I' of the semiconductor device shown in FIG. 1A. In the drawing, numeral 101 denotes a first semiconductor element, 102 denotes an electrode formed on an element forming surface of the semiconductor element 101, 103 denotes a second semiconductor element, 105 denotes a third semiconductor element, 104 and 106 denote electrodes formed on the respective semiconductor elements, 107 denotes a multi-layer wiring board, 108 denotes a circuit pattern formed on the surface layer of the multi-layer wiring board, and 109 denotes inner via holes. Numeral 110 denotes junctions which provide electrical connection between the semiconductor elements 101, 103, 105 and the circuit ...

embodiment 2

[0093] FIG. 4 is a cross sectional view of a module of the semiconductor device according to a second embodiment of the present invention. In the drawing, reference numerals identical to those of FIG. 1 denote the identical or corresponding portions. Numeral 112 denotes a mother wiring board whereon the semiconductor device is to be mounted, 113 denotes a circuit pattern formed in the surface layer of the mother wiring board, 114 denotes an Au wire for electrically connecting the multi-layer wiring board and the mother multilayer wiring board.

[0094] The module according to this embodiment is produced by such processes as shown in FIG. 4, the semiconductor device comprising the multi-layer wiring board 107, whereon the semiconductor elements which have passed electrical tests are mounted, is fastened on the mother multi-layer wiring board 112 at a specified position by bonding the back surface of the third semiconductor element 105 onto the mother multi-layer wiring board 112 by mean...

embodiment 3

[0099] FIG. 5 is a cross sectional view of a module of the semiconductor device according to the third embodiment of the present invention. In the drawing, reference numerals identical to those of FIG. 4 denote the identical or corresponding portions.

[0100] As can be seen in FIG. 5, a second semiconductor element 301 is mounted on the second side of the first wiring board 107, and the second semiconductor element 301 can be larger than the first semiconductor element 101, which is mounted on the first side of the first wiring board 107. In addition, the semiconductor device can include a third semiconductor element 302, which is also mounted on the first side of the first wiring board and is electrically connected to both the first and second semiconductor elements.

[0101] In the module according to this embodiment, the semiconductor device (including the first wiring board, the first semiconductor element, and the second semiconductor element) is mounted on the mother (second) multi...

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Abstract

A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.

Description

[0001] This application is a Divisional application of Ser. No. 10 / 337,879, now allowed, which is a Divisional application of Ser. No. 09 / 725,283, filed Nov. 29, 2000, now U.S. Pat. No. 6,525,414, which is a Continuation-in-Part application of Ser. No. 09 / 153,069, filed Sep. 15, 1998, now abandoned.[0002] 1. Field of the Invention[0003] The present invention relates to a semiconductor device formed by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring which uses inner via holes.[0004] 2. Description of the Related Art[0005] Attempts have been made to develop a semiconductor element in which a plurality of electronic circuits are incorporated in a single semiconductor element (for example IC chip, MIC chip and OEIC chip) in order to make electronic apparatuses having semiconductor elements used therein more compact. In practice, however, it is difficult to make a single semiconductor element having all necessary functions due to limitation...

Claims

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Application Information

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IPC IPC(8): H01L21/56H01L23/538H01L25/065H05K1/00H05K1/14H05K1/18H05K3/32H05K3/34H05K3/36
CPCH01L21/563H01L23/5385H01L25/0652H01L2224/16225H01L2224/73203H01L2224/73204H01L2924/01079H01L2924/15192H01L2924/19041H01L2924/19106H01L2924/19107H05K1/0284H05K1/141H05K1/147H05K1/189H05K3/328H05K3/3421H05K3/3442H05K3/363H05K3/368H05K2201/056H05K2201/10386H05K2201/10674H05K2203/049H05K2203/1572H01L24/48H01L2224/32225H01L2224/48091H01L2924/00H01L2924/00014H01L2224/45144H01L24/45H01L2924/14H01L2224/05571H01L2224/05573H01L2924/15174H01L2224/06131H01L2224/06135H01L2224/05599
InventorSHIRAISHI, TSUKASAMITANI, TSUTOMUAMAMI, KAZUYOSHIBESSHO, YOSHIHIRO
OwnerSHIRAISHI TSUKASA