Novel architecture to monitor isolation integrity between floating gate and source line
a floating gate and source line technology, applied in semiconductor/solid-state device testing/measurement, semiconductor device details, semiconductor/solid-state device testing/measurement, etc., can solve problems such as data value loss, ram cell discharge, and possible compromise of charge storage capacity
Inactive Publication Date: 2007-08-09
TAIWAN SEMICON MFG CO LTD
View PDF5 Cites 3 Cited by
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Benefits of technology
This approach enables the early detection of floating gate isolation issues, reducing scrap costs by identifying defects before completing the manufacturing process, thus saving resources and time.
Problems solved by technology
Once power is removed, the RAM cell discharges and the data value is lost.
However, the charge storage capability may be compromised.
The testing of nonvolatile memory arrays presents a unique testing problem because each cell in the array will need to be erased, programmed, and then read in each possible state (0 and 1).
The complete manufacturing process flow is therefore expensive and time consuming.
However, if a larger problem occurs such that redundancy is not sufficient to fix the problem, then the circuits are scrapped.
A wafer-wide problem may cause the entire wafer to be scrapped and thereby result in a loss of the entire processing investment.
It is found that a significant cause for such scrap is the integrity or quality of the dielectric isolation surrounding the floating gates.
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View moreImage
Smart Image Click on the blue labels to locate them in the text.
Smart ImageViewing Examples
Examples
Experimental program
Comparison scheme
Effect test
Embodiment Construction
[0028] The preferred embodiments of the present invention disclose a method to manufacture an integrated circuit device. A novel testing structure is disclosed for monitoring floating gate isolation integrity in a flash EEPROM process. A novel method to use the testing structure is disclosed. It should be clear to those experienced in the art that the present invention can be applied and extended without deviating from the scope of the present invention.
[0029] Referring now to FIGS. 1 through 11, a first embodiment of the present invention is illustrated. The embodiment shows a method to form a test structure for evaluating floating gate isolation in a memory device. Several important features of the present invention are shown and discussed below. The test structure is formed on an integrated circuit wafer. Preferably, the wafer is a monitoring wafer that is included as part of a production lot of wafers. For example, a production lot of 24 wafers might include a monitoring wafer....
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More PUM
Login to View More Abstract
A new method to form a floating gate isolation test structure in the manufacture of a memory device is achieved. The method comprises providing a substrate. A gate oxide layer is formed overlying the substrate. A floating gate conductor layer is deposited overlying the gate oxide layer. The floating gate conductor layer is patterned to expose the substrate for planned source regions. Ions are implanted into the exposed substrate to form the source regions. Contacting structures are formed to the source regions. Contacting structures are formed to the floating gate conductor layer.
Description
CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a divisional of U.S. patent application Ser. No. 10 / 833,179, filed Apr. 27, 2004, incorporated herein by reference.BACKGROUND OF THE INVENTION [0002] (1) Field of the Invention [0003] The invention relates to integrated circuit devices, and more particularly, to a method to monitor isolation integrity of the floating gate in the manufacture of a nonvolatile memory device. [0004] (2) Description of the Prior Art [0005] Memory devices are an important building block in the art of integrated circuit design and manufacture. Memory devices are used for temporary and permanent data storage in the integrated circuit or system. For example, a random access memory, or RAM, can be used to temporarily store data values. RAM memories are formed in static or dynamic forms. In either case, RAM requires a continuous power supply in order to retain the data. Once power is removed, the RAM cell discharges and the data value is lost. I...
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More Application Information
Patent Timeline
Login to View More Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L29/788H01L21/28H01L21/336H01L21/8247H01L23/544H10B69/00
CPCH01L21/28273H01L22/34H01L27/115H01L27/11521H01L2924/0002H01L2924/00H01L29/40114H10B69/00H10B41/30
InventorHSIEH, CHANG-JENSUNG, HUNG-CHENGHSU, TE-HSUN
OwnerTAIWAN SEMICON MFG CO LTD