Fractional frequency divider

Abstract

A divide-by-N / (N+0.5) frequency divider is disclosed. Two pairs of flip-flops are respectively triggered by an input clock and an inverted input clock, and a frequency-dividing selector is used to select one output of the two pairs of flip-flops as frequency-divided output signal. Two latches are respectively triggered by the input clock and the inverted input clock, and a modulus selector is used to select one output of the two latches. A modulus logic circuit determines being in either N frequency-dividing mode or (N+0.5) frequency-dividing mode based on a modulus control signal. A frequency-dividing logic circuit receives output of the modulus logic circuit and an inverted frequency-divided output signal to swallow half the input clock per output cycle in the (N+0.5) frequency-dividing mode, therefore obtaining division resolution of half the input clock.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention generally relates to a frequency divider, and more particularly to a dual-modulus divide-by-N / (N+0.5) frequency divider adaptable for a phase locked loop (PLL).[0003]2. Description of the Prior Art[0004]Phase locked loop (PLL) is widely utilized in integrated circuits or systems, such as communication systems, to synchronize the clocks of a receiver. FIG. 1 shows a block diagram of the PLL. A frequency divider 10 divides (or decreases) the frequency of the output signal of a voltage controlled oscillator (VCO) 12. The frequency-divided signal and a reference signal 14 are fed to a phase detector 16 to detect their phase difference. The detected difference signal passes through a loop filter 18 to have its noise filtered out, and then controls the frequency of the output signal of the VCO 12.[0005]The frequency divider 10 forms a negative feedback loop in the PLL of FIG. 1 to lock the VCO 12 at a mu...

AI Technical Summary

Benefits of technology

The solution enables efficient frequency division with reduced quantization noise power by 6 dB compared to conventional integer frequency dividers and allows for dynamic programming of division ratios, enhancing the frequency synthesizer's performance in complex communication systems.

Problems solved by technology

The integer frequency divider discussed above is not sufficient for modern complex communication systems, such as wireless communication systems.

For example, a fractional frequency divider (FIG. 4A) is disclosed in U.S. Pat. No. 5,729,179, which uses COUNTER and COINCIDENCE CIRCUIT, resulting in a circuit that is complicated, high-cost, and area consuming.

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