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Agile decoder

a decoder and encoder technology, applied in the field of decoders, can solve the problems of inability to change firmware in real-time, multiple chipsets can prove to be very expensive, and the relative length of firmware is difficult to achieve, and achieves the effects of reducing the number of decoders, and increasing the flexibility of decoding process

Inactive Publication Date: 2014-11-20
GVBB HLDG R L
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The decoder arrangement described in this patent allows for customization of decoding processes and can handle different sources and compression formats. It can decode video streams regardless of their native compression format or image size, and can decompress frames of different formats and composes them onto a common "canvas". The arrangement can also scale processing throughput by executing on multiple parallel threads.

Problems solved by technology

With hardware decoder implementations, decoding streams of different formats usually requires a different chipset for each stream type and relatively lengthy firmware downloads.
Multiple chipsets can prove to be very costly and making firmware changes in real-time becomes impractical.

Method used

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Embodiment Construction

[0008]FIG. 1 depicts a block schematic drawing of a decoder arrangement 10 in accordance with a preferred embodiment of the present principles for uncompressing a plurality of compressed video streams 111-11n, where n is an integer greater than zero. In practice, one or more of the video streams 111-11n can have a different format from the others. For example, one of the streams can take the form of an MPEG 2 stream, while another stream could take the form of a DV25 or DV50 stream. The particular format of each stream remains unimportant, as long as the particular format of the stream is known a priori.

[0009]In practice the decoder 10 of the present principles comprises a programmed processor 12, such as a microprocessor, microcomputer or the like, which operates in stages as described in greater detail below. When programmed to operate as a software decoder, the processor 12 will possess an input routing stage 13 that routes the compressed video streams 111-11n to an appropriate o...

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Abstract

A decoder arrangement (10) includes a processor (12) programmed to decode multiple streams (111-11n), including multiple streams of different formats. In terms of functionality, the decoder arrangement includes a routing stage (13) routes each streams to different decoder stages (141-14n), each capable of decoding a stream of a particular format to yield an uncompressed stream at its output. Each of plurality of buffer stages (161-16n) stores a successive frame of an uncompressed stream output by an associated decoder stage. An output stage scales and the frames stored by the buffer stages to a common size for input to a display device (22).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application Ser. No. 60 / 653,538, filed Feb. 16, 2005, the teachings of which are incorporated herein.TECHNICAL FIELD[0002]This invention relates to a decoder for decoding compressed streams.BACKGROUND ART[0003]Traditionally, video decoders have been hardware-based. In other words, typical video decoders take the form of discrete, stand-alone devices dedicated for this purpose. With hardware decoder implementations, decoding streams of different formats usually requires a different chipset for each stream type and relatively lengthy firmware downloads. Multiple chipsets can prove to be very costly and making firmware changes in real-time becomes impractical.[0004]Thus a need exists for a decoder arrangement that overcomes the disadvantages of the prior art.BRIEF SUMMARY OF THE INVENTION[0005]Briefly, in accordance with a preferred embodiment of the present p...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H04N19/44
CPCH04N19/00533H04N19/12H04N19/44H04N19/42
Inventor DELUCA, MICHAEL ANTHONY
Owner GVBB HLDG R L
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