Methods of forming epi semiconductor material on a thinned fin in the source/drain regions of a finfet device

Abstract

One illustrative method disclosed includes, among other things, forming a gate around an initial fin structure and above a layer of insulating material, and performing a fin trimming process on an exposed portion of the initial fin structure in the source / drain region so as to produce a reduced-size fin portion positioned above a surface of a layer of insulating material in the source / drain region of the device, wherein the the reduced-size fin portion has a second size that is less than the first size. In this example, the method also includes forming a conformal epi semiconductor material on the reduced-size fin portion and forming a conductive source / drain contact structure that is conductively coupled to and wrapped around the conformal epi semiconductor material

Description

BACKGROUND OF THE INVENTION1. Field of the Invention[0001]The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to methods of forming epi semiconductor material on a thinned fin in the source / drain regions of a FinFET device and the resulting device.2. Description of the Related Art[0002]In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially field effect transistors (FETs), are provided and operated on a restricted chip area. FETs come in a variety of different configurations, e.g., planar devices, FinFET devices, nanowire devices, etc. These FET devices are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the ...

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