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Clock master-slave phase difference automatic measurement and compensation process

A technology for automatic measurement and phase difference, applied in time division multiplexing systems, electrical components, multiplexing communications, etc., and can solve problems such as high cost, complicated circuits, and complicated operations.

Inactive Publication Date: 2008-04-16
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the above-mentioned patent application also needs to be equipped with devices such as a phase detector, which has the defects of complex circuit, high cost, and complicated operation.

Method used

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  • Clock master-slave phase difference automatic measurement and compensation process
  • Clock master-slave phase difference automatic measurement and compensation process
  • Clock master-slave phase difference automatic measurement and compensation process

Examples

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Embodiment Construction

[0027] The preferred embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

[0028] Fig. 1 shows the flow chart of the first embodiment of the present invention, including measuring step S10 and compensating step S12, in measuring step S10, in the master clock unit that is in the active state and is in the standby state that is provided with redundant wiring After the standby clock unit is powered on, the standby clock unit automatically measures the phase difference between the main and standby clocks in real time; in the compensation step S12, phase compensation is performed on the standby clock unit according to the phase difference, so that the output phases of the main and standby clocks are synchronized.

[0029] After the main and stan...

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Abstract

The invention discloses a method of automatic detection and compensation of the main / standby phase diversity of clocks. The method comprises the following steps: a detection step, a main clock unit at main status and a standby clock unit at standby status, provided with redundant layout, powered on, the standby clock unit automatically detects the phase difference of the main clock unit in real time. A compensation step, the standby clock unit is processed with the phase compensation according to the phase difference to enable the output phase of the main / standby clocks to be synchronous. According to the invention, the automatic detection of the phase diversity and the compensation of the output phase of the standby clock unit can be reached by layout and software configuration without any extra part. The invention can enable the phase of the output ends of the main / standby clock units to be consistent, thereby guaranteeing the phase continuity when main / standby switching. The consistency of the main / standby output phase guarantees the least effect on the system when main / standby switching and no slip code / bit error of service card created because of clock units switching.

Description

technical field [0001] The invention relates to a network communication clock synchronization technology, more specifically, a processing method for synchronizing main and standby clocks and realizing end-to-end phase automatic measurement and compensation of main and standby outputs. Background technique [0002] Communication equipment generally adopts active-standby redundancy to improve system reliability, and the clock is a very important part of communication services, so the active-standby working mode is generally adopted in system design. In a synchronous digital communication network, the synchronization between network element nodes in the network is realized by a clock unit. Each network element node is configured as two active and standby clock units for each other. In order to realize the smooth switchover of the active and standby clocks, the service board will not generate bit errors due to clock fluctuations. The phase continuity index of the active and stan...

Claims

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Application Information

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IPC IPC(8): H04J3/08H04J3/06
Inventor 屠亚奇
Owner ZTE CORP
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