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Access buffering mechanism and method

A technology of a buffering device and a buffering method, applied in memory systems, memory address/allocation/relocation, instruments, etc., can solve problems such as increasing system overhead, and achieve the effect of improving performance and reducing resource overhead

Active Publication Date: 2011-04-13
LOONGSON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Compared with the present invention, it achieves effective use of memory access bandwidth by rearranging the order of access, but increases system overhead

Method used

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  • Access buffering mechanism and method
  • Access buffering mechanism and method

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Embodiment Construction

[0065] In order to make the purpose, technical solution and advantages of the present invention clearer, a memory access buffer device and method of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0066] A kind of memory access buffer device and method of the present invention, its basic principle is, at first cache the read request on the read channel, then send the read request longer than the original request length to the memory controller without wasting the effective bandwidth of DDR, if Before the read data is returned, if there is a new request on the read channel that falls within the relevant address of this access, then there is no need to send a read request to the memory controller, and only need to record the corresponding information...

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Abstract

The invention discloses a device for buffering access storage and a method thereof. The method comprises the following steps: an up read channel receives read requests sent by a CPU, caches the read requests meeting buffer operation conditions, and transmits a read request for reading more data, and the read request contains the read address length of the read requests meeting buffer operation conditions; for the read requests not meeting buffer operation conditions, the read requests which do not meet buffer operation conditions are directly transmitted through a down read channel; the down read channel receives the read data return, and returns the read data of the read requests to the CPU after the read data is returned to the cache as the circumstances may require; or the data are directly returned to the CPU. The invention has the advantages that the effective transmission tape width of memory is increased and the access storage delay is reduced.

Description

technical field [0001] The invention relates to the field of memory control, in particular to a memory access buffer device and method. Background technique [0002] The current mainstream memory standards are DDR2 memory and DDR3 memory, where DDR refers to Double DataRate, double data rate, that is, data is transmitted twice in each clock cycle. In this way, the actual data transmission of DDR (here generally refers to DDR2 / DDR3, the same below) can work at a very high operating frequency, but due to the high data transmission frequency of DDR and the relatively low internal operating frequency, a kind of It is called burst transmission mode (BURST). [0003] The burst transmission mode refers to a mode in which adjacent storage units in the same row continuously perform data transmission, and the number of storage units (columns) involved in continuous transmission is the burst length (Burst Lengths, BL). In the DDR2 standard, a BL is 4, that is, a read-write access res...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/08G06F12/0877
Inventor 王焕东唐丹胡伟武
Owner LOONGSON TECH CORP
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