Forward error correction encoding for multiple link transmission compatible with 64b/66b scrambling

Abstract

The present invention discloses a Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B / 66B encoding standard for transmission on Serializer / Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B / 66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an errorreplicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable. In addition, the packet can betransported across multiple serial links for higher bandwidth applications without a degradation of the code efficiency. The Hamming code can be generated from any irreducible polynomial, such as H(x) = x<10> + x<3> + 1. The BIP code is chosen to be of degree 6 to fit with 64B / 66B scrambling polynomial and is represented by B(x) = x<6> + 1.

Description

technical field [0001] The technical field of the invention relates to high-speed digital communication systems, and more particularly to methods for correcting the multiplication of single bit errors by bit (bit) error spreading due to self-synchronized scrambling. Improved coding techniques to enhance the reliability of the transmitted signal. Background technique [0002] In digital communication systems, the transmission of data is subject to corruption and errors due to the presence of noise in the communication channel. The scrambling used to help accurately receive the signal at the destination introduces additional errors through a process known as error diffusion. In such systems, redundant parity bits are commonly used at the source to encode the transmitted signal to allow error correction. The digital bit stream is typically parsed into n-bit fixed-length datawords based on the maximum length of the clock signal timing reference that the system receiver can ext...

AI Technical Summary

Problems solved by technology

The disadvantage of this scheme is that errors cannot be corrected when packets are transmitted over multiple bit lines, as described above

[0018] Other applications of FEC codes do not fully address the effect of bit error diffusion attributable to the descrambling process

For example, the Network Processing Forum (NPF2003.320.00) paper (NPF2003.320.00) submitted by Xilinx discloses a 64B / 66B encoder which cannot overcome the bit error multiplication problem caused by descrambling

Another approach has been taken by the Optical Internetworking Forum in document OIF2004.229.03 by PMC-Sierra, Xilinx and Sandia International Laboratories, which also does not overcome the doubling problem

Similarly, commonly assigned U.S. Patent Application 2004 / 0193997A1 discloses a method for combining a simple FEC code with scrambling and descrambling functions to reduce bit error propagation, but requires data packets to be transmitted over a single serial link, so multiple The bit error information is propagated on packets