Method and device for enhancing frequency stability of target clock

Abstract

The invention discloses a method for enhancing frequency stability of a target clock under the maintaining state, comprising the following steps: inputting another frequency-fixed clock to a phase locked loop based on a source clock as the standard clock, and regulating, according to the source clock, a frequency division number for performing frequency division on the frequency-fixed clock; performing phase discrimination on the frequency-divided target clock and the frequency-divided frequency-fixed clock, and filtering the phase discrimination result and then controlling an adjustable clock module to output the target clock. The invention further discloses a device for enhancing frequency stability of the target clock under the maintaining state, the target clock has high frequency stability under the maintaining state by using the method and the device, and the cost is relatively reduced.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a method and a device for improving the frequency stability of a target clock in a holding state. Background technique [0002] At present, when adjusting the clock of the communication system, it is necessary to ensure that the destination clock is synchronized with the source clock, that is, when the source clock fails or is lost, the destination clock is not affected and the original output accuracy is maintained. To synchronize the destination clock with the source clock, usually use figure 1 A phase-locked loop with a holdover control block as shown, as figure 1 As shown, the phase-locked loop includes: a source frequency division module, a phase detection module, a filter module, a hold control module, an adjustable clock module and a destination frequency division module. The adjustable clock module outputs the destination clock, and the destination clock is fed b...

AI Technical Summary

Problems solved by technology

At this time, due to the failure or loss of the source clock, then figure 1 The phase-locked loop shown cannot continue to work, and the control module can only adjust the output clock required by the adjustable clock module. Therefore, it is necessary to maintain a high degree of stability between the control module and the adjustable clock module. The stability of a module does not meet the requirements, and the phase-locked loop cannot work at this time, then the final output destination clock cannot be synchronized with the source clock

[0004] Although the existing phase-locked loop can achieve high frequency stability of the target clock under the holding state, it also has the following defects: 1) because the stability of the adjustable clock module directly affects the stability of the target clock, so The adjustable clock module needs to maintain a high degree of stability. Usually, a voltage-controlled constant temperature crystal oscillator (OCXO) is used. The OCXO needs a constant temperature of about 100°C, which not only wastes costs but also accelerates the aging speed of the device and is easily damaged.

In addition, the adjustable clock module needs to have a voltage control adjustment function, and the relationship between the voltage control function of the OCXO and the temperature is complicated. If the temperature compensation effect is not good, it is difficult to achieve high stability.

2) Maintaining the output stability of the control module also affects the stability of the target clock. To achieve high stability requires the support of a high-stable voltage reference source, which is not easy to obtain and also wastes cost

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