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Method and device for coding quasi-cyclic low density parity check codes

A technology of low-density parity and coding method, which is applied in the field of quasi-cyclic low-density parity-check code coding method and device, which can solve the problems of large coding delay and achieve fast coding speed, reduce chip area, and occupy less resources.

Active Publication Date: 2014-12-10
ZTE CORP +1
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Problems solved by technology

[0007] The present invention provides a quasi-cyclic low-density parity-check code encoding method and device to solve the problem of large encoding delay in the prior art

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  • Method and device for coding quasi-cyclic low density parity check codes
  • Method and device for coding quasi-cyclic low density parity check codes
  • Method and device for coding quasi-cyclic low density parity check codes

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Embodiment Construction

[0052] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0053] In order to solve the problem of large coding delay in the prior art, the present invention provides a quasi-cyclic low-density parity-check code coding method and device.

[0054] Such as figure 1 As shown, a kind of quasi-cyclic low-density parity-check code encoding method provided by the present invention specifically includes:

[0055] Step S101, bit preprocessing step, this step is used for when information bit sequence input coder, one road is u...

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Abstract

The invention discloses a method and a device for coding quasi-cyclic low density parity check codes. The method comprises the following steps of: bit preprocessing: outputting one path of information bit sequences input into a coder as an information bit of a code word, calculating the other path of the information bit sequences to obtain a middle sequence needed by coding, and storing the middle sequence into a coder RAM (random access memory) array; check sequence v(0) computation: performing mode 2 sum operation on a stored value read from a corresponding RAM in the RAM array to obtain v(0), writing one path of the v(0) into the RAM array, and outputting the other path of the v(0) as a check bit; and remaining check sequence computation: reading the middle sequence and the v(0) stored in the RAM array on the basis of a remaining check sequence recursion formula, performing parallel computation in a pipeline mode to obtain the remaining check sequences, and outputting the remaining check sequences. By means of the method, transmitted information bits can be coded in real time, a part of the transmitted information bits is not needed to be stored before computation, and the coding speed is high.

Description

technical field [0001] The present invention relates to the field of communication technology, in particular to a quasi-cyclic low density parity check code (Quasi-Cyclic Low Density Parity Check, QC-LDPC) encoding method and device. Background technique [0002] LDPC code is a linear block code based on sparse check matrix proposed by Gallager in 1962; in 1996, MacKay and Neal rediscovered LDPC code and proved that it has performance close to the Shannon limit. Some existing communication systems, such as DVB and WiMAX, all use LDPC codes as channel codes. For the structural characteristics of the check matrix H of LDPC codes, LDPC codes can be divided into LDPC codes constructed by quasi-cyclic matrix (QC-LDPC) codes and LDPC codes constructed by ordinary matrices. The check matrix H of the QC-LDPC code can be regarded as a fundamental matrix H b Extended to get, H b The element value in represents a cyclic shift matrix of a z*z unit matrix, and if the element is -1, it...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11
Inventor 张涛
Owner ZTE CORP
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