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Decoding method and decoding device of IRA (irregular repeat-accumulate) series LDPC (low density parity check) codes

An LDPC code and decoding technology, applied in the field of LDPC decoding method and decoding device, can solve the problems of cumbersome read and write control of memory, large sparse matrix, etc. Effect

Active Publication Date: 2014-03-05
GUANGZHOU HAIGE COMM GRP INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The reason why the traditional LDPC code is not widely used is because it has multiple defects, and the decoder design has the following defects: 1. The check matrix of the traditional LDPC code has random characteristics, and it needs to store a Non-sparse matrix, but in order to pursue the performance of LDPC codes, the code length is required to be long enough, which leads to the sparse matrix will be very large, which brings great problems to storage; 2. The decoder throughput and implementation of traditional LDPC codes are complex If serial decoding is used, the throughput must be very low. If full parallel or partial parallel decoding is used, the read and write control of the memory must become quite cumbersome.
The existing LDPC code decoders have not been able to meet the needs of the market in terms of data rate and multi-code rate compatibility.

Method used

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  • Decoding method and decoding device of IRA (irregular repeat-accumulate) series LDPC (low density parity check) codes
  • Decoding method and decoding device of IRA (irregular repeat-accumulate) series LDPC (low density parity check) codes
  • Decoding method and decoding device of IRA (irregular repeat-accumulate) series LDPC (low density parity check) codes

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Embodiment

[0085] like image 3 As shown, the decoder of the present invention includes p main memory bank units MMB numbered from 0 to p-1 (p≥1), p processing units PU from 0 to p-1 (p≥1), 0 to p-1 (p≥1) p forward update memories, address parameter table memory, memory address read controller, shift parameter table memory, cyclic shifter and control unit CU.

[0086] The control unit CU is respectively connected to p processing units PU, address parameter table memory, memory address reading controller, and shift parameter table memory;

[0087] The memory address reading controller is respectively connected to p main memory bank units MMB;

[0088] Each main memory bank unit MMB is connected to the processing unit PU with the same number as it;

[0089] The address parameter table memory is also connected with the memory address reading controller;

[0090] The cyclic shifters are respectively connected to p main memory bank units MMB;

[0091] The cyclic shifters are respectively ...

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Abstract

The invention discloses a decoding method of IRA (irregular repeat-accumulate) series LDPC (low density parity check) codes. The method mainly comprises the following steps of (1) inputting channel information; (2) identifying whether the process of channel information inputting is finished, if not, repeating the steps (1) and (2); if so, performing the step (3); (3) decoding iteration process: including an information node processing step and a check node processing step; wherein in the iteration process, a calculated result of the last iteration is used in this iteration; and (4) outputting the decoding result in sequence; the steps (1) to (3) form a first grade stream line and the step (4) forms a second grade stream line; the second grade stream line is started after the first grade stream line is ended, at the same time, the first grade stream line processes the decoding of the next code word synchronously. Compared with the prior art, the decoding method and decoding device provided by the invention can be used for improving the velocity of convergence of the decoding algorithm and the throughput of a decoder, and have the advantages of high data velocity and multi-code rate compatibility.

Description

technical field [0001] The invention relates to the communication field, in particular to an LDPC decoding method and a decoding device. Background technique [0002] Communication systems usually use channel coding technology to ensure the reliability of communication in noisy channels. For example, in a satellite communication system, due to the influence of geographical and environmental factors, there are a large number of noise sources. These communication channels have their theoretical maximum communication capacity (also known as the Shannon limit), which can be expressed in terms of bit rate (bps) at a specific signal-to-noise ratio (SNR). Therefore, the forward error correction code (FEC) is designed to pursue the maximum bit rate close to the Shannon limit. One such code that approaches the Shannon limit is the low-density parity-check (LDPC) code. [0003] LDPC code is a kind of linear block code, which can obtain performance close to the Shannon limit in a la...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11
Inventor 陆连伟
Owner GUANGZHOU HAIGE COMM GRP INC
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