Decoding method and decoding device of IRA (irregular repeat-accumulate) series LDPC (low density parity check) codes
An LDPC code and decoding technology, applied in the field of LDPC decoding method and decoding device, can solve the problems of cumbersome read and write control of memory, large sparse matrix, etc. Effect
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[0085] like image 3 As shown, the decoder of the present invention includes p main memory bank units MMB numbered from 0 to p-1 (p≥1), p processing units PU from 0 to p-1 (p≥1), 0 to p-1 (p≥1) p forward update memories, address parameter table memory, memory address read controller, shift parameter table memory, cyclic shifter and control unit CU.
[0086] The control unit CU is respectively connected to p processing units PU, address parameter table memory, memory address reading controller, and shift parameter table memory;
[0087] The memory address reading controller is respectively connected to p main memory bank units MMB;
[0088] Each main memory bank unit MMB is connected to the processing unit PU with the same number as it;
[0089] The address parameter table memory is also connected with the memory address reading controller;
[0090] The cyclic shifters are respectively connected to p main memory bank units MMB;
[0091] The cyclic shifters are respectively ...
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