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A Constructing Method of Steiner Tree with Obstacles in Large-Scale Integrated Circuit Design

A technology of large-scale integrated circuits and construction methods, applied in computing, electrical digital data processing, special data processing applications, etc., can solve problems such as low solution quality

Inactive Publication Date: 2016-08-10
FUZHOU UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This type of algorithm is easy to fall into a local optimal solution, resulting in low solution quality

Method used

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  • A Constructing Method of Steiner Tree with Obstacles in Large-Scale Integrated Circuit Design
  • A Constructing Method of Steiner Tree with Obstacles in Large-Scale Integrated Circuit Design
  • A Constructing Method of Steiner Tree with Obstacles in Large-Scale Integrated Circuit Design

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Embodiment Construction

[0078] In order to implement the present invention concretely, we give the following description about the practice of the invention.

[0079] The computer system implementing the present invention: the method for constructing the right-angled Steiner tree around obstacles in the large-scale integrated circuit design designed by the present invention will be implemented on a specific computer system, and the computer system is specifically described as follows.

[0080] A personal computer (Intel Core I5 ​​3.2GHz processor, 16GB memory);

[0081] CentOS 6.4 operating system;

[0082] C++ programming language;

[0083] Gcc 4.4.7 compiler, gdb debugging tool, etc.

[0084] The problem of constructing a rectangular Steiner tree around obstacles is a typical combinatorial optimization problem, and its problem model is specifically described as follows:

[0085] The given wire mesh information includes the two-dimensional coordinate information of each wire mesh pin on the plane...

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Abstract

The invention relates to an obstacle-avoiding rectilinear Steiner tree construction method in large-scale integrated circuit design, and belongs to the field of integrated circuit computer aided design, in particular to the field of circuit wiring design in physical design of large-scale integrated circuits. The obstacle-avoiding rectilinear Steiner tree construction method is characterized in that firstly, a wiring problem wiring diagram is built according to escape graph theory; secondly, a quasi-optimal feasible solution is constructed by the aid of edges of the wiring diagram by taking an artificial bee colony optimization method as a basic framework; thirdly, a global search strategy, a local search strategy based on key nodes, codes based on key nodes and an encoder based on an improved heuristic algorithm are designed in order to implement the artificial bee colony optimization method. The obstacle-avoiding rectilinear Steiner tree construction method can be used for constructing a high-quality obstacle-avoiding rectilinear Steiner tree, and is applicable to solving the problems of an obstacle-avoiding minimum rectilinear Steiner tree and a non-obstacle-avoiding minimum rectilinear Steiner tree in circuit wiring of the integrated circuit design.

Description

technical field [0001] The invention relates to a method for constructing a right-angle Steiner tree around obstacles in large-scale integrated circuit design, belonging to the field of computer-aided design of integrated circuits, especially the field of circuit wiring design in physical design of large-scale integrated circuits. Background technique [0002] In the physical design of large-scale integrated circuits, the basic problem solved by circuit routing is to use a right-angle Steiner tree to connect all pins of a wire net in the routing area, and make the tree bus length as small as possible. Aiming at this problem, people are currently mainly studying the obstacle-avoiding rectilinear Steinerminimal tree (OARSMT). The rectilinear Steiner minimaltree (RSMT) problem is a simplified special case of the OARSMT problem, and it has been proved to be an NP-complete problem. With the rapid development of integrated circuit technology, a large number of macro cells, IP mod...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 张浩叶东毅
Owner FUZHOU UNIV
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