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Parallel Encoding of Non-Binary Linear Block Codes

A kind of coder, the technique of bit coding, applied in the field of coding of non-binary linear block code

Active Publication Date: 2019-04-16
XILINX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Maintaining such high line rates while using serial input is very difficult to achieve due to the complex logic involved in calculating the parity bits

Method used

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  • Parallel Encoding of Non-Binary Linear Block Codes
  • Parallel Encoding of Non-Binary Linear Block Codes
  • Parallel Encoding of Non-Binary Linear Block Codes

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Embodiment Construction

[0016] Embodiments will be described below with reference to the accompanying drawings. It should be noted that the figures are not drawn to scale and that components of similar structure or function are denoted by the same reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the various embodiments. They are not intended as an exhaustive description of the invention or as a limitation on the scope of the claimed invention. Furthermore, the illustrated embodiments need not have all of the aspects or advantages shown. An aspect or advantage described in connection with a particular embodiment is not necessarily limited to that embodiment and may be practiced in any other embodiment, even if not so stated. Furthermore, references throughout this specification to "some embodiments" or "other embodiments" mean that a particular property, structure, material, or characteristic described in connection wit...

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Abstract

An encoder module includes P / L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P / L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.

Description

[0001] Reservation of Rights in Copyrighted Material [0002] The present invention part of this patent document contains copyrighted material. The copyright owner has no objection to the facsimile reproduction by anyone of said patent document or patent disclosure as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyrights whatsoever. technical field [0003] The present application relates generally to encoding of non-binary linear block codes, and in particular to systems and methods for implementing parallel encoding for non-binary linear block codes. Background technique [0004] Linear Forward Error Correction (FEC) codes have widespread application in communication and mass storage systems where data integrity and correctness must be protected. Linear block FEC takes blocks of data bits and protects the blocks of data by adding multiple redundant bits. Typically, an encoder calculates these redundancy bits, and a d...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/15H03M13/13
CPCH03M13/13H03M13/05H03M13/1134H03M13/1137H03M13/1171H03M13/134H03M13/1515H03M13/21H03M13/6502H03M13/6561
Inventor 卡利安娜·克里薛南谭海若
Owner XILINX INC
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