Semiconductor memory device, refresh control system, and refresh control method

Abstract

A semiconductor memory device includes a normal command generation unit suitable for generating a normal refresh command in response to a refresh command; a smart command generation unit suitable for performing a counting operation on the refresh command to generate a plurality of smart refresh commands which are activated at a predetermined period; and a refresh operation unit suitable for performing a refresh operation in response to the normal refresh command and the plurality of smart refresh commands, wherein the smart command generation unit resets the counting operation when entering into the refresh operation.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2013-0149923 filed on Dec. 04, 2013, the entire contents of which are hereby incorporated by reference. technical field [0003] Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor memory device performing a refresh operation, a refresh control system, and a refresh control method. Background technique [0004] Generally, a semiconductor memory device such as a double data rate synchronous dynamic random access memory (DDR SDRAM) includes a plurality of banks for storing data, and each of the plurality of banks includes tens of millions of multiple memory unit. Each memory cell is composed of a cell capacitor and a cell transistor, and the semiconductor memory device stores data by charging or discharging charges in the cell capacitor. [0005] It would be ideal if the...

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Problems solved by technology

However, since an increase in the number of times refresh operations are performed deteriorates the operating efficiency of the semiconductor memory device, there is a limit to the number of times refresh operations can be performed

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