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Multiplication-free quasi-cyclic matrix serial multiplier for WPAN (wireless personal area network)

A quasi-circular matrix and multiplication technology, applied in the field of channel coding, can solve the problems of high circuit power consumption, high cost, large registers, etc., and achieve the effect of reducing power consumption, simple structure, and reducing logic resources

Inactive Publication Date: 2015-12-02
RONGCHENG DINGTONG ELECTRONICS INFORMATION SCI & TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

One of the disadvantages of this scheme is that a large number of registers are required, which will inevitably lead to large power consumption and high cost of the circuit.

Method used

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  • Multiplication-free quasi-cyclic matrix serial multiplier for WPAN (wireless personal area network)
  • Multiplication-free quasi-cyclic matrix serial multiplier for WPAN (wireless personal area network)
  • Multiplication-free quasi-cyclic matrix serial multiplier for WPAN (wireless personal area network)

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specific Embodiment approach

[0028] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, so as to define the protection scope of the present invention more clearly.

[0029]Since the generator polynomial f of the circulant matrix i,j Rotating right n bits is equivalent to rotating it left b-n bits, ie Then equation (8) can be rewritten as

[0030] m i F i , j = e i × b f ...

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Abstract

The invention provides a multiplication-free quasi-cyclic matrix serial multiplier for a WPAN (wireless personal area network). The multiplier is used for multiplication of a vector m and a quasi-cyclic matrix F during approximate lower triangle encoding of QC-LDPC (quasic-low-density parity-check) codes with a 1 / 2 code rate under the standard of WPAN and comprises two generator polynomial lookup tables used for prestoring cyclic matrix generator polynomials and 21-bit null vectors in 1 / 2 code rate matrix F, two 21-bit binary adders for performing modulo-two adding on generator polynomial lookup table output and shift register content and two 21-bit shift registers for storing results obtained after cyclic shift left of the sum of 21-bit binary adders for one bit respectively. According to the quasi-cyclic matrix serial multiplier, multiplication is eliminated, and the quasi-cyclic matrix serial multiplier has the advantages of few logic resources, simple structure, low power consumption, low cost and the like.

Description

technical field [0001] The invention relates to the field of channel coding, in particular to a quasi-circular matrix serial multiplier in WPAN standard 1 / 2 code rate QC-LDPC approximate lower triangular coding. Background technique [0002] Low-Density Parity-Check (Low-Density-Parity-Check, LDPC) code is one of efficient channel coding techniques, and QC-LDPC (Quasic-LDPC, QC-LDPC) code is a special LDPC code. Both the generation matrix G and the check matrix H of the QC-LDPC code are arrays composed of circulant matrices, which have the characteristics of a segmented cycle, so they are called QC-LDPC codes. The first row of the circulant matrix is ​​the result of the cyclic right shift of the last row by 1 bit, and the remaining rows are the result of the cyclic right shift of the previous row by 1 bit. Therefore, the circulant matrix is ​​completely characterized by its first row. Usually, the first row of a circulant matrix is ​​called its generator polynomial. [000...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/523
Inventor 张鹏
Owner RONGCHENG DINGTONG ELECTRONICS INFORMATION SCI & TECH CO LTD
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