Successive approximation type analog-to-digital converter weight calibration method

Abstract

The invention discloses a successive approximation type analog-to-digital converter weight calibration method. The weight calibration method comprises the following steps that: in a capacitor array including n capacitors having capacitances disposed from a high bit to a low bit: Cn-1, Cn-2, and the like, C0; the weight of the ith capacitor is represented by BWi and conforms to the condition: as shown in the specification; the weight of the ith capacitor Ci is obtained by gradual calibration of the weights of the capacitors Ci-1, Ci-2, and the like, C0; a calculation method is as follows: as shown in the specification; b0, b1, and the like, bi-1 are digital codes obtained during calibration of Ci and corresponding to the capacitors C0, C1, and the like, Ci-1; BW0 is a preset value, whereini, j belongs to {0, and the like, n}, and n is a positive integer; after the weight calibration is completed, the successive approximation type analog-to-digital converter obtains non-binary redundancy digital codes bn-1, bn-2, and the like, b0 for an analog input; and a binary quantitative result is obtained according to a formula as shown in the specification. According to the successive approximation type analog-to-digital converter weight calibration method, by use of the redundancy characteristic of a non-binary SARADC (Successive Approximation type Analog-to-Digital Converter), a high bit weight to be calibrated is less than a sum of low bit weights, and is calibrated by using an existing structure of the SARADC and a conversion mechanism; the high bit is calibrated by the low bit; under the condition that the area and the complexity of a circuit are not increased as far as possible, a bit weight of a capacitor is precisely calibrated, and high-precision analog-digital conversionis realized.

Description

technical field [0001] The invention relates to the technical field of electronic circuits, in particular to a method for calibrating the weight of a successive approximation analog-to-digital converter. Background technique [0002] An analog-to-digital converter (ADC) converts an analog signal into a digital signal and acts as a bridge from the outside world to a digital computer. With the development of science and technology, high-precision ADCs have become one of the essential chips in the fields of industry, medical treatment, and automobiles. High-precision ADCs (16-24 bits) are usually implemented with successive approximation analog-to-digital converters (SARADC) and sigma-delta ADCs. SARADC has the advantages of low latency and easy multi-channel sharing, and is very suitable for multi-channel real-time sampling. Capacitance-based SARADC compares the input voltage signal and the voltage value generated by the capacitor array one by one, from high to low, to obtai...

AI Technical Summary

Problems solved by technology

Such an implementation method increases the complexity and area of ​​the circuit due to the need to increase the calibration capacitor array and the control circuit.

Moreover, the usual calibration technique is based on the SARADC with binary weights, if there is a conversion error due to noise, dynamic errors during the conversion process, this error will not be corrected

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