Entry data acquisition method and apparatus, and communication device

Abstract

Embodiments of the invention provide an entry data acquisition method and apparatus, and a communication device, belonging to the technical field of communication. The method comprises steps of acquiring entry data from a switch chip through a first bus by a programmable logic device, and storing the entry data in an FIFO queue; when it is determined that the FIFO queue is full, sending a read notification to a processor through a second bus, so as to enable the processor to read the entry data from the FIFO queue. The processor acquires the entry data rapidly through the second bus, so that low cost is maintained, further, the processor refreshes internal entry data within a shorter period, is lowered in resource overhead effectively, can put more resources in other businesses, and is improved in overall performance.

Description

technical field [0001] The present application relates to the technical field of communications, and in particular, to a method, device, and communications equipment for obtaining entry data. Background technique [0002] With the development of communication technology, users' business requirements for data transmission bandwidth and delay are getting higher and higher. Routers and switches are used as pipeline equipment for data transmission, and the efficiency of data processing and table entry data directly affects the efficiency of data transmission. bandwidth and latency. [0003] The purpose of the entry data synchronization mechanism is to read the entire hardware entry data existing in the switch chip into the processor CPU to establish a mapping table, for example, to read the MAC address entry into the CPU to establish a mapping table, so that the upper layer software When performing Layer 2 address (that is, hardware MAC address) operations, it is not necessary ...

AI Technical Summary

Problems solved by technology

[0005] Although the maximum rate of the switch chip SPI management interface can support a rate of 40MHz, the maximum rate of the processor's SPI controller bus is only 5MHz. If the processor manages the switch chip at a rate of 5MHz, the processor will update the MAC address table or MIB data once. The table will consume resources for a long time, resulting in a waste of processor resources, and the refresh time of table items in the processor is too slow, which affects the data forwarding efficiency and cannot meet the requirements of some real-time forwarding business applications

[0006] In order to avoid the above problems, the traditional solution is to replace the processor with a higher SPI bus rate, but this will obviously greatly increase the design cost, and at the same time, the processor reads the large-capacity data table in the switching chip through the serial interface, and it will also continuously It consumes a lot of processor resources and affects the reading efficiency of table entries

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