Fast classification method, method and device for EEG signals based on FPGA

A technology of rapid classification of EEG signals, applied in the field of brain-computer interface, to achieve the effects of avoiding violation of timing constraints, avoiding calculation delays, large scalability and flexibility

Inactive Publication Date: 2019-02-22
SHANDONG NORMAL UNIV
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  • Abstract
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Problems solved by technology

[0008] Aiming at the deficiencies in the prior art and solving the problem of how to balance flexibility and reconfigurability for different network structures in the process of EEG signal classification, one or more embodiments of the present disclosure provid

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  • Fast classification method, method and device for EEG signals based on FPGA
  • Fast classification method, method and device for EEG signals based on FPGA
  • Fast classification method, method and device for EEG signals based on FPGA

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Embodiment Construction

[0063] The technical solutions in one or more embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in one or more embodiments of the present disclosure. Obviously, the described embodiments are only part of the implementation of the present invention. example, not all examples. Based on one or more embodiments of the present disclosure, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts fall within the protection scope of the present invention.

[0064] It should be pointed out that the following detailed description is exemplary and intended to provide further explanation to the present application. Unless otherwise specified, all technical and scientific terms used in this embodiment have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0065] It should be noted that the terminology used here is ...

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Abstract

The invention discloses a fast classification method of EEG signals based on FPGA, a realization method and a device thereof. The hard logic of a CNN network structure model suitable for the classification of EEG signals is constructed on FPGA, and the convolution operation is converted into matrix multiplication. The IP cores of each layer in the CNN network structure model are established, and the IP cores of each layer in the CNN network structure model are connected by using the synchronous data flow method, and AXI4-Streaming register chip is inserted between the adjacent IP cores; the EEG training data is received, the floating-point data is converted to a fixed-point number with a preset number of bits, training the CNN network structure model, adjusting the CNN network structure model weight value until the highest classification accuracy model is obtained, and the trained model parameters are stored in DDR memory, so as to obtain FPGA which can realize the fast classificationof EEG signals, and the fast classification of EEG signals is carried out by using the CNN network structure model.

Description

technical field [0001] The technical field to which the present disclosure belongs is brain-computer interface (BCI), and relates to an FPGA-based fast classification method, implementation method and device for EEG signals. Background technique [0002] The statements in this section merely provide background information related to the present disclosure and do not necessarily constitute prior art. [0003] Brain-computer interface technology involves the fields of computer communication and control technology, neurology, biomedical engineering, and rehabilitation medicine. It interprets user intentions by analyzing and processing EEG signals. At present, EEG signals generated by different stimuli can be collected through special equipment. To directly control peripheral devices through the brain, it is necessary to accurately identify and classify the EEG signals collected by the equipment. [0004] At present, the acquisition mode of EEG signals is mostly realized throug...

Claims

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Application Information

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IPC IPC(8): G06N3/02
CPCG06N3/02
Inventor 杨济民郑文凯刘丹华刘杰
Owner SHANDONG NORMAL UNIV
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