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Chip testing method

A chip testing and chip technology, applied in static memory, instrument, sorting, etc., can solve problems such as memory damage

Pending Publication Date: 2021-02-02
ONE TEST SYST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The embodiment of the present invention is to provide a chip testing method to improve the existing memory testing equipment, after repeatedly installing and removing the memory on the electrical connection seat provided in the oven or the electrical connection seat in the low temperature room During the process, the memory is easily damaged

Method used

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Embodiment Construction

[0055] Please also refer to figure 1 , figure 2 and image 3 , figure 1 It is a schematic diagram of the chip testing system disclosed by the present invention, figure 2 It is a schematic block diagram of the chip testing system disclosed by the present invention, image 3 It is a schematic diagram of the chip testing device disclosed in the present invention. The chip testing system E disclosed by the present invention is used for testing multiple chips C. The chip testing system E includes: a central control device E1, a chip mounting device E2, at least one chip testing device 1, a plurality of environmental control devices E3, a transfer device E4 and a sorting device E5.

[0056] The central control device E1 is connected to the chip mounting equipment E2, multiple environmental control equipment E3, transfer equipment E4, and sorting equipment E5, and the central control device E1 can control the operation of each equipment; the central control device E1 is, for e...

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Abstract

The invention discloses a chip testing method, which is suitable for a chip testing system, and comprises a chip installation step: installing a plurality of chips on a plurality of electric connection seats of a chip testing device through chip installation equipment; a moving-in step: moving the chip testing device carrying the plurality of chips to one accommodating chamber of one environment control equipment; a temperature adjusting step: controlling a temperature adjusting device corresponding to the accommodating chamber to operate so as to enable the plurality of chips to be in an environment with a preset temperature; and a test step: supplying power to the chip testing device arranged in the accommodating chamber, so that each test module performs a predetermined test program onthe chips on the plurality of electric connection seats connected with the test module.

Description

technical field [0001] The invention relates to a chip testing method, in particular to a chip testing method applied to testing memory. Background technique [0002] Existing memory testing equipment, when performing high temperature, low temperature and burn-in (Burn-In) tests on memory, is to repeatedly install and remove the memory in the electrical connection socket set in the oven or in the low temperature chamber In this way, during the repeated installation and removal of the memory, unexpected problems will easily occur, such as damage to the pins of the memory. Contents of the invention [0003] The embodiment of the present invention is to provide a chip testing method to improve the existing memory testing equipment, after repeatedly installing and removing the memory on the electrical connection seat provided in the oven or the electrical connection seat in the low temperature room During the process, the memory is easily damaged. [0004] One embodiment of ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/56B07C5/344
CPCG11C29/56016B07C5/344
Inventor 蔡振龙基因·罗森塔尔
Owner ONE TEST SYST
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