Integrated circuit modeling acquisition method and system based on abstract syntax tree

Abstract

The invention discloses an integrated circuit modeling acquisition method and system based on an abstract syntax tree, and belongs to the technical field of integrated circuit design. The method comprises the following steps: acquiring a Verilog HDL source code project file of the large-scale integrated circuit, and extracting .V files with a mutual dependency relationship; analyzing the .V file into an abstract syntax tree, and exporting the abstract syntax tree into a .Json file; traversing the file meeting the standard json format to obtain data information, and storing the data information into a data structure; and analyzing the data structure to obtain an analysis result, and exporting the analysis result as a TXT file. Due to the fact that the abstract syntax tree does not depend on specific grammar and language details, after the source code is converted into the abstract syntax tree, many operations can be conducted on the abstract syntax tree, and then the flexibility and efficiency of modeling design of a super-large-scale integrated circuit can be improved.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design, and more specifically relates to an integrated circuit modeling and design method and system based on an abstract syntax tree. Background technique [0002] VLSI generally refers to integrated circuits with relatively high integration such as field programmable logic gate arrays, system-on-chips, and large-capacity static random access memories. With its increasing scale, hierarchical and modular design has become the mainstream. Verilog HDL is one of the languages ​​commonly used in circuit design. It is a language that describes the structure and behavior of digital system hardware in text form. It can represent logic circuit diagrams, logic expressions, and logic completed by digital logic systems. Features. In the process of design and coding, the use of each design level, each module unit, and each type of port is very important information, so frequent statistics are nee...

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Problems solved by technology

[0003] Aiming at the above defects or improvement needs of the prior art, the present invention provides a method and system for obtaining integrated circuit modeling based on an abstract syntax tree. design status, resulting in technical problems with insufficient efficiency of modeling acquisition or design

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