SPI slave interface with adjustable SDO data phase

Abstract

The invention discloses an SPI slave interface with an adjustable SDO data phase. The SPI slave interface comprises a register, a clock gating unit, a clock selection unit, a delay control unit, N signal selection units and N delay units, the delay control unit is connected with an external controller and is provided with N + 1 stealing ports, and N output ports of the delay control unit are correspondingly connected with the control ends of the N signal selection units respectively; the serial clock is input into two input ends of the clock selection unit, and an output end of the clock selection unit is connected with a clock port of the register; the N delay units are sequentially connected end to end, the N signal selection units are sequentially connected end to end, the output end of the first signal selection unit outputs data in the register to the SDO, and the output ends of the N delay units are correspondingly connected with the input ends of the (N-1) signal selection units respectively. According to the invention, the output phase of the SDO signal of the slave can be adjusted in real time, so that the slave can correctly read data, and the reading accuracy is improved.

Description

technical field [0001] The invention relates to the field of digital circuit design, in particular to an SPI slave interface with adjustable SDO data phase. Background technique [0002] The SPI (Serial Peripheral Interface, Serial Peripheral Interface) protocol stipulates that data is prepared on the falling edge of SCLK (serial clock), and data is collected on the rising edge of SCLK. Therefore, conventional SPI slave interfaces prepare data on the falling edge of SCLK. [0003] However, when the SCLK frequency of the conventional SPI slave interface is high, timing problems often occur due to the delay between the boards. When the master reads the data from the slave, it often collects wrong data, and the data transmitted by the slave misses the data collected by the master. point. Such as figure 1 shown in figure 1 Among them, Tm2s is the data transmission delay from the master to the slave, and Ts2m is the data transmission delay from the slave to the master; among ...

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