Packaging method and device for reusable UVM verification environment, equipment and medium

A technology for verifying the environment and encapsulation methods, applied in the computer field, can solve problems such as failure to comply with reusable structures, unfavorable code reuse, time-consuming and labor-intensive problems, and achieve the effects of reducing debugging difficulties, making code reusable easy, and ensuring tape-out time

Pending Publication Date: 2022-01-07
杭州云合智网技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] (1) Need to manually write each component or object class file, which is time-consuming and laborious
[0006] (2) Although there is already a set of UVM frameworks, there are differences in the code writing habits of everyone in the team, and it is still difficult to locate problems when they occur
[0007] (3) When verifying complex RTL, existing code needs to be reused, but because everyone does not follow a unified reusable structure, there are many problems in the actual reusable process
[0029] It can be seen that there are a lot of class files that need to be manually written, and the codes of the input and output interfaces are mixed together. The code writing method is relatively free, which is not conducive to code reuse in the top-level verification environment.

Method used

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  • Packaging method and device for reusable UVM verification environment, equipment and medium
  • Packaging method and device for reusable UVM verification environment, equipment and medium
  • Packaging method and device for reusable UVM verification environment, equipment and medium

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Embodiment Construction

[0071] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0072] In order to better understand the technical solutions of the present invention, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0073] It should be clear that the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the ar...

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Abstract

The invention provides a packaging method and device for a reusable UVM verification environment, equipment and a medium, and the method comprises the steps: executing a configured first script file to achieve the automatic packaging of an interface, so as to generate an agent packaging file, wherein the first script file is configured with a data member and a bit width on an interface, and the agent packaging file is a subclass of uv_magent in a UVM class library file and belongs to a verification component type; executing a configured second script file to perform semi-automatic packaging on the agent packaging file so as to generate an env packaging file, wherein the second script file comprises a path where an agent contained in specified instantiation is located, a path where the second script file is located, and the number of required instantiation; and generating a UVM verification environment according to the agent packaging file and the env packaging file. The working efficiency of developers is greatly improved, and the effect of accelerating the project progress is achieved, so that the tape-out time of the chip project is ensured.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to a packaging method, device, equipment and medium for a reusable UVM verification environment. Background technique [0002] Usually, when verifying RTL, the widely used verification methodology is UVM (Universal Verification Methodology), which is a verification platform developed based on TLM (Transaction-Level Modeling) communication. Simply put, it is a class library file that can help verification developers easily build a configurable and reusable verification environment. This methodology has encapsulated many low-level interfaces into individual objects, and developers only need to use them according to the grammatical rules. [0003] Such as figure 1 as shown, figure 1 Typical architecture for existing UVM verification platforms. In theory, only the UVM agent, scoreboard and basic transaction (sequence), as well as the sequence and sequencelibrary containing...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F8/35G06F8/36
CPCG06F8/36G06F8/35
Inventor 闵捷喻明皓马骁
Owner 杭州云合智网技术有限公司
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