Device and method for submitting instructions out of order

Abstract

The invention discloses a device and a method for submitting instructions out of order. Comprising an instruction cache memory, an instruction fetching module in signal connection with the instruction cache memory, an instruction queue module and a CPU branch processing module which are in signal connection with the instruction fetching module, a decoder in signal connection with the instruction queue module, and a uop queue module in signal connection with the decoder, the renaming register is in signal connection with the uop queue module, the distribution module is in signal connection with the renaming register, the scheduling program module is in signal connection with the distribution module, the execution units are in signal connection with the scheduling program module, and the execution units are in signal connection with a reordering buffer area. Wherein one execution unit is in signal connection with a data buffer area. According to the method and the device, the instructions which are not executed in the assembly line can be submitted out of order, and performance loss caused by access delay of the instructions or L2 / memory is reduced.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a device and method for submitting instructions out of order. Background technique [0002] The development of microprocessors has made tremendous progress in just a few decades. Continuously improve the performance of the processor from the aspects of hardware architecture, technology and combination of software and hardware. The hardware architecture has gone from single-issue scalar to multi-issue superscalar; from the initial 3-stage pipeline to dozens of pipelines; from sequential execution of instructions to out-of-order execution of instructions; from no cache to multi-level cache storage structure; from physical single core From physical multi-core (CMP, Chip Multi-Processors) and logical single-core to logical multi-core (SMT, Simultaneous Multi-Threading); even cluster systems for supercomputing, the processor's instruction-level parallelism and thread-level parallel...

AI Technical Summary

Problems solved by technology

Load, store, AMO, and UC type instructions need to access memory. When a DCACHE miss occurs, it may need to access L2, L3, and memory, which will consume hundreds of blocks of clock cycles, which will affect the follow-up of this instruction. instruction execution efficiency

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