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Multifunctional DMA transmission method and device and storage medium

A transmission method and multi-functional technology, applied in the field of DMA data transmission, which can solve problems such as single function

Pending Publication Date: 2022-03-25
SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The traditional DMA controller can only perform the operations related to the above data transfer, and its function is relatively single. If it is necessary to perform a consistency check on the transferred data, an additional hardware unit for calculating the CRC check code is required to participate.

Method used

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  • Multifunctional DMA transmission method and device and storage medium
  • Multifunctional DMA transmission method and device and storage medium
  • Multifunctional DMA transmission method and device and storage medium

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0043] refer to figure 1 As shown, the embodiment of the present invention provides a multifunctional DMA transmission method, including:

[0044] S100, the CPU configures corresponding DMA descriptor parameters in the descriptor register according to DMA service requirements, wherein the DMA descriptor parameters include mode parameters, and the mode parameters include a first mode, a second mode, a third mode, and a fourth mode; In the specific implementation process, refer to Figure 4 As shown, the CPU supports at least four descriptor registers, and supports parallel configuration of DMA descriptor parameters including four mode parameters through four different descriptor registers.

[0045] During the specific implementation process, the DMA descriptor parameters including the first mode also include: source address, destination address and transmission data length.

[0046] The DMA descriptor parameters including the second mode also include: data pattern, data patte...

Embodiment 2

[0066] refer to image 3 As shown, the embodiment of the present invention provides a device for realizing multi-function DMA transmission, including:

[0067] A first configuration module, the first configuration module is configured to configure DMA descriptor parameters of the DMA descriptor according to DMA service requirements;

[0068] A second configuration module, the second configuration module is used to configure the data capacity of the burst mode;

[0069] Specifically, see Figure 4 As shown, the first configuration module includes a CPU and a descriptor register, and the second configuration module includes a CPU and a burst mode transmission capacity register. According to the DMA service requirements, the CPU configures the corresponding DMA descriptor parameters in the descriptor register, and configures the data capacity of the burst mode according to the memory bit width or the bus bit width. The data capacity of the burst mode does not exceed the memory ...

Embodiment 3

[0076] An embodiment of the present invention provides a storage medium for implementing a multifunctional DMA transmission method, wherein the storage medium for implementing a multifunctional DMA transmission method stores at least one instruction, and reads and executes the instruction to implement the multifunctional DMA transmission method.

[0077] In the present invention, control the DMA controller to execute different data processing strategies by including the DMA descriptor of different mode parameters; when the mode parameter of the DMA descriptor is the first mode, the DMA controller transmits the data of the source address to the destination address, Realize data movement; when the mode parameter of the DMA descriptor is the second mode, the DMA controller repeatedly transmits the data pattern to the destination address to realize the setting of the data pattern; when the mode parameter of the DMA descriptor is the third mode, the DMA control The controller perfo...

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Abstract

The invention relates to a multifunctional DMA transmission method and device and a storage medium. According to the method, a CPU configures corresponding DMA descriptor parameters in a descriptor register according to DMA service requirements, the DMA descriptor parameters comprise mode parameters, and the mode parameters comprise a first mode, a second mode, a third mode and a fourth mode; the DMA controller obtains DMA descriptor parameters from the descriptor register to form DMA descriptors; the DMA controller arbitrates and selects a DMA channel for data processing, and obtains a DMA descriptor of the corresponding channel; obtaining mode parameters in the DMA descriptor, and determining a data processing strategy according to the type of the mode parameters; and substituting other parameters in the DMA descriptor into a preset data processing strategy corresponding to the mode parameter for execution. According to the method, different data processing strategies are formed based on DMA descriptors containing different mode parameters and related parameters, so that multiple functions such as data migration, data style setting, calculation of data CRC check codes and data transmission between caches are realized.

Description

technical field [0001] The invention relates to the field of DMA data transmission, in particular to a multifunctional DMA transmission method, device and storage medium. Background technique [0002] DMA (Direct Memory Access: direct memory access) is a data transfer technology that directly exchanges data with the system memory without going through the CPU. It can realize memory-to-memory, device-to-memory, and memory-to-device-to-data transmission, greatly reducing the workload of the CPU. , Data transfer through DMA solves the problem of excessive consumption of CPU resources by data transfer, allowing the CPU to focus more on calculation and control. [0003] In the prior art, the DMA process is implemented by a DMA controller. The DMA controller has the following functions: it can send a system hold (HOLD) signal to the CPU and propose a bus takeover request; after the DMA controller receives the permission signal from the CPU to take over, the DMA replaces the CPU f...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/28G06F11/10
CPCG06F13/28G06F11/1004
Inventor 周云龙宋杰
Owner SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
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