Reed-solomon decoder key equation and error value solving-optimizing circuit

Abstract

To solve problems of the large size of circuit board and its high cost in the design of Leed Solomon decoder circuit using the traditional technique, this invention provides an optimum solving circuit of the key equation and error value of Leed Solomon decoder. The combination of selector, multiplier, adder, 3-way selector, giving original value and 3-state function circuit, flip-flop, latch, static memory, select and reciprocating circuit and select / flip-flop circuit realizes the solving error position polynomial (x), error value polynomial (x) and final error value. It utilizes reusing the single circuit to realize the function, which needs usually two circuits. Therefore, the circuit size, complicacy and the cost are as reduced as possible.

Description

technical field

[0001] The invention relates to a Reed Solomon decoder of an error correction device for transmitting data in digital communication, in particular to a key equation and an error value solving and optimizing circuit of the Reed Solomon decoder. Background technique

[0002] There are many coding methods in the field of channel coding, which can be divided into block codes and convolutional codes according to the different constraints between information symbols and check symbols. The Reed-Solomon code is a kind of block code. The characteristic of this coding method is that the information is divided into separate data segments, and at the same time, redundant protection information is added to each data segment according to the coding algorithm to form A self-contained codeword is used for transmission.

[0003] The unit of Reed-Solomon code (hereinafter referred to as RS code) is composed of a section of multi-bit bytes. Even if an error occurs in every bit...

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