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Reed-solomon decoder key equation and error value solving-optimizing circuit

A technology of Reed-Solomon decoder and error value, which is applied in the direction of data representation error detection/correction, error correction/detection using block codes, electrical components, etc., and can solve problems such as increasing circuit area and increasing circuit cost

Inactive Publication Date: 2007-03-28
SOUTHEAST UNIV
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  • Abstract
  • Description
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AI Technical Summary

Problems solved by technology

The circuit design of the prior art is to realize the two steps of 2 and 4 with one circuit respectively, which will greatly increase the circuit area and increase the circuit cost

Method used

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  • Reed-solomon decoder key equation and error value solving-optimizing circuit
  • Reed-solomon decoder key equation and error value solving-optimizing circuit
  • Reed-solomon decoder key equation and error value solving-optimizing circuit

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Embodiment Construction

[0034] As shown in Figure 1, a key equation and error value solving optimization circuit of a Reed-Solomon decoder includes a selector 1, a multiplier 2, a selector 3, an adder 4, a selector 5, a multiplier 6, and a three-way Selector 7, initial value assignment and tri-state function circuit 8, selector 9, flip-flop 10, selector 11, latch 12, static memory 13, selection and reciprocal circuit 14, selection and trigger circuit 15 and static memory 16. Error value solves coefficient signal X j 1-b Connect to an input terminal of selector 1, and the output of selector 1 is connected to an input terminal of multiplier 2, and at the same time, the error value polynomial solves the signal Ω(X j -1 ) is connected to an input end of the selector 3, the output of the selector 3 is connected to the other input end of the multiplier 2, and the output of the multiplier 2 is respectively connected to an input end of the adder 4 and an input end of the selector 5, and the adder The outp...

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Abstract

To solve problems of the large size of circuit board and its high cost in the design of Leed Solomon decoder circuit using the traditional technique, this invention provides an optimum solving circuit of the key equation and error value of Leed Solomon decoder. The combination of selector, multiplier, adder, 3-way selector, giving original value and 3-state function circuit, flip-flop, latch, static memory, select and reciprocating circuit and select / flip-flop circuit realizes the solving error position polynomial (x), error value polynomial (x) and final error value. It utilizes reusing the single circuit to realize the function, which needs usually two circuits. Therefore, the circuit size, complicacy and the cost are as reduced as possible.

Description

technical field [0001] The invention relates to a Reed Solomon decoder of an error correction device for transmitting data in digital communication, in particular to a key equation and an error value solving and optimizing circuit of the Reed Solomon decoder. Background technique [0002] There are many coding methods in the field of channel coding, which can be divided into block codes and convolutional codes according to the different constraints between information symbols and check symbols. The Reed-Solomon code is a kind of block code. The characteristic of this coding method is that the information is divided into separate data segments, and at the same time, redundant protection information is added to each data segment according to the coding algorithm to form A self-contained codeword is used for transmission. [0003] The unit of Reed-Solomon code (hereinafter referred to as RS code) is composed of a section of multi-bit bytes. Even if an error occurs in every bit...

Claims

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Application Information

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IPC IPC(8): H03M13/05H03M13/09H04L1/00
Inventor 吴建辉吴俊晏飞李红茆邦琴
Owner SOUTHEAST UNIV
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