Wafer level hermetic sealing method
a technology of hermetic sealing and semiconductor devices, which is applied in the direction of fluid speed measurement, instruments, coatings, etc., can solve the problems of high percentage of chips becoming defective, equipment used in a general semiconductor process cannot be used during the sawing process, and the movement structure must be carefully handled. to achieve the effect of promoting the adhesion of adhesives
Inactive Publication Date: 2005-07-28
SAMSUNG ELECTRONICS CO LTD
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- Abstract
- Description
- Claims
- Application Information
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Benefits of technology
The present invention provides a method for sealing semiconductor devices at a wafer level, which prevents them from being affected by moisture or particles and at a low temperature. This is suitable for devices such as MEMS structures that are sensitive to high temperatures. The method involves forming adhesives on the wafer and lid wafer, aligning them, and sealing them together. The adhesives are made of metals such as In, Sn, Ag, Pb, Zn, Au, Bi, Sb, Cd, Ga, and Cu or their alloys. The method can also include forming electrical connectors on the wafer and forming a hole in the lid wafer for connecting them to the outside. The technical effect of this invention is to provide a reliable and efficient way to seal semiconductor devices at a wafer level.
Problems solved by technology
The resulting moving structures must be carefully handled because these structures can be damaged or rendered completely inoperative by a single microscopic particle.
Here, a high percentage of the chips become defective due to the particles generated during the sawing process.
The equipment used in a general semiconductor process cannot be used during the sawing process, while additional equipment for fabricating devices such as MEMS is required.
This results in an increase in the production cost.
Here, the chip is exposed to the outside environment, and moisture or particles can attach to the chip if the anti-stiction film becomes contaminated.
These factors can damage the device or make the device completely inoperable.
As described above, performing the hermetic sealing process in a chip state is costly as well as labor and time intensive.
An increase in cost is attributable to additional equipment needed to carefully handle the MEMS devices or chips having moving structures.
In addition, maintaining a multiple work environment such as two anti-stiction coating lines and two testing lines is also costly, and labor and time intensive.
This process is slow because the area of the package to be coated is large, thereby requiring a large amount of time to coat the anti-stiction film.
Accordingly, these methods are not appropriate for devices such as MEMS, which use aluminum actuators having a relatively low fusion temperature.
However, even a temperature of about 450□C. is too high for aluminum actuators and high pressure, which may negatively affect the device, is required.
Method used
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[0023] Reference will now be made in detail to the present preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures.
[0024] Referring to FIGS. 3A through 3E, in the wafer level sealing method of the present invention, semiconductor devices are formed at a wafer level, additional lids are also formed at a wafer level, and the semiconductor devices and the lids are sealed at a low temperature using an adhesive.
[0025] As shown in FIG. 3A, semiconductor devices 12 are formed on a wafer 10. Electrical connectors 15 for electrical connection with the outside may be formed.
[0026] As shown in FIG. 3B, a lid wafer 30 for transceiving an optical signal is prepared apart from the wafer 10. Adhesives 35 are formed to bond the wafer 10 and the lid wafer 30 together....
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Abstract
A device that is hermetically sealed at a wafer level or a method of hermetically sealing a device, which is sensitive to high temperatures or affected by heating cycles. Semiconductor devices are formed on a wafer. A lid wafer is formed. Adhesives are formed in a predetermined position over the wafer and / or the lid wafer. The wafer and the lid wafer are sealed by the adhesives at the wafer level. The sealing may be performed at a low temperature using a solder to protect the devices sensitive to heat. The sealed devices are diced into individual chips. In the wafer level hermetic sealing method, a sawing operation is performed after the devices are sealed. Therefore, the overall processing time is reduced, devices are protected from the effects of moisture or particles, and devices having a moving structure, such as MEMS devices, are more easily handled.
Description
CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a divisional of application Ser. No. 09 / 984,734 filed on Oct. 31, 2001, now pending, the content of which is incorporated by reference herein. [0002] This application claims the benefit of Korean Application No. 2001-5256, filed Feb. 3, 2001, in the Korean Industrial Property Office, the disclosure of which is incorporated by reference herein.BACKGROUND OF THE INVENTION [0003] 1. Field of the Invention [0004] The present invention relates to a semiconductor device with a wafer level hermetic seal and a method of hermetically sealing a device at the wafer level. More particularly, the present invention relates to a method of hermetically sealing a semiconductor device which is at a wafer level where the device sensitive to high temperatures or affected by a heat cycle can be thermally sealed at a low temperature and is not affected by moisture or particles. [0005] 2. Description of the Related Art [0006] Referring to F...
Claims
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IPC IPC(8): H01L23/14B81B7/00B81C1/00H01L21/50H01L23/00H01L23/04H01L23/10
CPCB81B7/0077B81C1/00269H01L2924/12041H01L2924/10253H01L2924/01322B81C1/00357B81C2201/019H01L21/50H01L23/10H01L2224/48227H01L2924/01079H01L2924/16235H01L24/48H01L2924/00H01L2224/05599H01L2224/45099H01L2224/85399H01L2924/00014H01L2224/45015H01L2924/207H01L23/04
InventorCHO, CHANG-HOSHIN, HYUNG-JAEKIM, WOON-BAE
OwnerSAMSUNG ELECTRONICS CO LTD