Self-organizing network with chip package having multiple interconnection configurations

Abstract

In general, embodiments of the present invention provide a chip package with multiple TSV configurations. Specifically, the chip package typically includes a backend layer (e.g., metal interconnect layer); a substrate coupled to the backend layer; a set (at least one) of backend side interconnects extending (e.g., angularly) from a side surface of the backend layer to a bottom surface of the backend layer; a set of optional vertical TSVs extending from a top surface of the backend layer through the substrate; and a network organizer positioned in the substrate organizer for handling communications made using the set of backend side interconnects and the set of vertical TSVs. A set of connections (e.g., controlled collapse chip connections (C4s) can be positioned adjacent to any of the vias to provide connectively to other hardware elements such as additional chip packages, buses, etc. Among other things, the use of backend side interconnects allows maximum surface area of the chip package to be utilized and provides increased reliability. These advantages are especially realized when used in conjunction with vertical TSVs.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This patent document is a divisional application of commonly owned and co-pending patent application Ser. No. 12 / 974,165, entitled “SELF-ORGANIZING NETWORK WITH CHIP PACKAGE HAVING MULTIPLE INTERCONNECTION CONFIGURATIONS”, filed on Dec. 21, 2010.TECHNICAL FIELD[0002]The present invention relates to networks and chip packages. Specifically, the present invention relates to a self-organizing network with a 3-dimensional (3D) chip package having backend side interconnects and / or through silicon vias (TSVs).BACKGROUND OF THE INVENTION[0003]In electronics, a through silicon via (TSV) is a vertical electrical connection (via) passing completely through a silicon wafer or die. TSV technology is important in creating 3D packages and 3D integrated circuits. A 3D package (System in Package, Chip Stack MCM, etc.) contains two or more chips (integrated circuits) stacked vertically so that they occupy less space. An alternate type of 3D package can be ...

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