Network-on-chip for neurological data

a neuronal data and network-on-chip technology, applied in the field of neuronal data network-on-chip network, can solve the problems of recording such data, processing it, and packetizing it, and achieve the effects of improving the accuracy of neuronal data processing

Active Publication Date: 2021-01-14
NEURALINK CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent describes a system and method for processing neurological voltage signals using a chip with an array of amplifiers and electrodes. The chip has a configur circuitry that receives program instructions and instructs the amplifiers which signals to pass on. The data packets, which contain the signals from the amplifiers, are then passed on to a merge circuitry. The merge circuitry can vary the length of the data packets depending on the number of amplifiers involved. The data can also be compressed before being passed on. The technical effects of this invention include improved accuracy and efficiency in processing neurological voltage signals.

Problems solved by technology

But recording such data, packetizing it, and processing it can be difficult, if the number of electrodes is more than just a few.

Method used

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  • Network-on-chip for neurological data
  • Network-on-chip for neurological data
  • Network-on-chip for neurological data

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Embodiment Construction

[0017]Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a sufficient understanding of the subject matter presented herein. But it will be apparent to one of ordinary skill in the art that the subject matter may be practiced without these specific details. Moreover, the particular embodiments described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known data structures, timing protocols, software operations, procedures, and components have not been described in detail so as not to unnecessarily obscure aspects of the embodiments of the invention.

Overview

[0018]Brain interfaces with computer systems may require the use of electrodes to receive neurological impulses and turn them into voltage readings or signals. Som...

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Abstract

The embodiments disclosed herein relate to chips used to receive and process neurological events in brain matter as captured by electrodes. Such chips may include an array of amplifiers and electrodes to receive neurological voltage signals, the chip including a config circuitry in communication with the array of amplifiers and a controller, the config circuitry configured to receive program instructions and instruct the amplifiers of a voltage threshold and instruct the controller to pass on signals from only specific rows and columns of amplifiers, the controller in communication with the array of amplifiers, the controller configured to packetize the neurological voltage signals into data packets.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS[0001]This application is a continuation of U.S. patent application Ser. No. 16 / 354,059, filed Mar. 14, 2019, which claims the benefit of U.S. Provisional Application No. 62 / 644,217, filed Mar. 16, 2018, which is incorporated by reference in its entirety for all purposes.STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT[0002]NOT APPLICABLEFIELD[0003]This application relates to the field of computing devices, systems-on-chip, inter-chip networks, data packetizing, and data traffic flow.BACKGROUND[0004]Interfaces between living brain tissue and computer components have evolved over time. Certain interfaces allow electrodes into brain tissue to record neurological events. But recording such data, packetizing it, and processing it can be difficult, if the number of electrodes is more than just a few. Some examples include the “sewing machine” arrangement of electrode placement as described in Internationa...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G06F13/38G06N3/063A61B5/04
CPCG06F13/38G06N3/063G06F2213/0038A61B5/04001A61B5/04004A61B5/0015A61B5/24A61B5/30
InventorSEO, DONGJINMEROLLA, PAUL A.MONGE OSORIO, MANUEL ALEJANDRO
OwnerNEURALINK CORP