4results about How to "Avoid decoding errors" patented technology

The present invention provides a method and system for optimizing DS decoding of a high-speed SpaceWire bus, including: a synchronous sampling module, a skew jitter error compensation module, an asynchronous buffer module and a DS decoding module; the synchronous sampling module synchronizes the input DS signal to the system sampling clock after three signal latches, and transmits the signal to the skew jitter error compensation module for data sampling compensation, and transmits the signal to the DS decoding module and the asynchronous buffer module after judging the valid data flag; the asynchronous buffer module shifts the buffer, converts the storage and marks the valid length of the data; the DS decoding module decodes, performs serial shift operations, and outputs data words and control words. The present invention realizes three-level synchronous sampling, reduces the risk of signal competition and risk; the bus has a high rate, and can realize the decoding function of the bus at 200Mbps~400Mbps; sampling compensation for sampling errors caused by DS signal jitter and skew, and at the same time adopts an optimized DS decoding algorithm to solve decoding errors caused by signal jitter and skew.

The embodiment of the invention provides a data processing method and device, electronic equipment and a computer readable storage medium, and relates to the technical field of multimedia. The method comprises the following steps: if a decoding state change instruction for a decoder is detected, determining a current first decoding state of the decoder; wherein the first decoding state comprises a preset decoding state or an accelerated decoding state; the preset decoding state is realized by performing loop filtering processing on a data frame of which loop filtering is started in a coding process; the accelerated decoding state is realized by not carrying out loop filtering processing on a target frame in the data frame code stream; the target frame comprises a non-reference frame with inter-frame reference in the data frame code stream; determining a second decoding state of the decoder based on the unit decoding duration of the decoder and the first decoding state; and decoding the data frame to be decoded according to the second decoding state. According to the embodiment of the invention, the decoding state of the decoder is adaptively converted through the unit decoding duration of the current decoder, and the decoding efficiency is effectively improved.

The present invention relates to a digital circuit device for processing a high-frequency radio frequency identification chip demodulation blind area, comprising: a radio frequency data processing circuit, which uses a radio frequency output clock to sample and process radio frequency output data, so that the timing relationship between the processed data and the clock is relatively fixed; a radio frequency clock processing circuit, which uses the output signal of the radio frequency data processing circuit to perform a logical operation on the radio frequency output clock, and the processed output clock signal can effectively avoid burrs; a combined output circuit, which performs a logical operation on the output data and the output clock according to the logical requirements of the demodulation digital circuit for the clock signal and the data signal, so that its output signal meets the logical requirements of the demodulation digital circuit for correct decoding. The output data and the output clock processed by this device have a stable timing relationship, and can effectively avoid burrs on the clock, which can meet the needs of the subsequent demodulation digital circuit for stable operation, thereby effectively avoiding the blind area phenomenon of the high-frequency radio frequency identification chip.

Embodiments of the present application provide a sampling point determination method, device, equipment, storage medium and program product. A calibration signal of a backlight driver is obtained. The calibration signal includes at least first bit data and second bit data. The duration of the first level period of the first bit data is greater than the duration of the first level period of the second bit data. The first level period of the second bit data is a pre-stage period. The duration of the data period of the first bit data is determined according to the difference between the duration of the first level period of the first bit data and the duration of the first level period of the second bit data. Then, the duration of the data period of the first bit data and the product of any value within the preset range of the sampling ratio are added to the pre-stage period to determine the sampling point of each bit data in the backlight driver. Thus, the sampling point can be ensured to fall in the data period in the case of signal distortion, the calculation accuracy of the sampling point is improved, and data decoding errors are avoided.