Method for forming grid medium layer and estimating its electrical parameter
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Publication Date
- 2009-11-18
- Estimated Expiration
- Not applicable · inactive patent
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Abstract
Description
technical field
[0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for evaluating electrical parameters of a gate dielectric layer and forming a gate dielectric layer. Background technique
[0002] With the development of semiconductor technology, more devices need to be integrated in a limited area, and the size of corresponding devices needs to be reduced. With the help of advanced photolithography technology, such as 193nm, 157nm and immersion exposure technology, the gate length representing the semiconductor process level can reach 90nm, or even 65nm. The turn-on voltage applied to the gate gradually becomes smaller, and correspondingly, the thickness of the gate dielectric layer becomes thinner, so as to increase the response speed of the device. In particular, for the current semiconductor process of 90nm and below, the thickness of the gate oxide has been reduced to 5nm or even smaller. Chinese patent appli...