Method for testing time failure of communication system and its device

Abstract

A method for detecting time fault of communication system includes generating synchronous time calibration information separately by master / standby clock processing single boards, utilizing consistence-detecting module to compare said calibration information outputted by said single boards and reporting alarm if deviation is existed on said calibration information outputted by said single boards, analyzing out which single board occurred with abnormal in combining on current service situation and deciding whether master / standby clock processing single boards should be rotated or not.

Description

technical field [0001] The invention relates to a communication technology, in particular to a method and device for detecting system time faults in a communication system. Background technique [0002] Typically, synchronous distributed network systems maintain synchronization between system clocks using time information provided by Global Positioning System (GPS) communication satellites. Due to the atomic clock-like accuracy of time synchronization information among various data provided by GPS communication satellites, a synchronous distribution network system receives time information from a GPS receiver and synchronizes the entire system based on a clock signal obtained from the time information. In some business applications of the communication system, it is necessary to obtain the current absolute time information of the system immediately (that is, from the absolute zero time of the system (0:00 on January 6, 1980) to the current time), and the time accuracy obtain...

AI Technical Summary

Problems solved by technology

Even if there is an abnormality in the satellite receiver on a clock processing board, for example, there is a certain deviation between the output 1PPS and the standard, so the 1PPS synchronization pulse output by the clock board will follow the deviation, or due to the abnormality of the board itself, such as the synchronization of the board The 1PPS pulse hardware is abnormal, which causes the output to deviate from the standard by a certain phase

Since each clock processing board operates independently and cannot detect its own abnormality, even though the system has implemented active backup for the clock processing board, the system cannot detect the abnormality and cannot perform active / standby switchover to solve the problem of the system. existing problems

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